4-6 GHz low-power integer frequency dividers applied in wireless sensor networks in 0.18 μm CMOS

摘要

This paper presents the design of two integer frequency dividers, divider-by-2 and programmable divider, which are both applied in wireless sensor networks. The divider-by-2 is used to generate the local oscillator signal for mixers and adopts the common-gate flip-flop with dynamic load. The programmable divider consists of prescaler and programmable counter. All the dividers are fabricated in 0.18 μm CMOS process and can work normally at 1 V in the range of 4-6 GHz. The phase noise of the divider-by-2 is -131.69 dBc/Hz at 3.5 MHz and its core power cost is 1.5 mW. The ratio of the programmable divider can be varied from 2403 to 2480 and its input sensitivity can be as small as -38 dBm at 5 GHz.