A Simple Metal-Semiconductor Substructure Model for the Thermal Induced Fatigue Simulation in Power Integrated Circuits

摘要

Thermal Induced Plastic Metal Deformation (TPMD) in a double-diffused metal-oxide semiconductor (DMOS) power device is highly dependent on the design and material properties of the metallization system corresponding to the technology in which the device is fabricated. To analyse and understand the interactions between the temperature, stress and strain distribution in the metallization system, a simple substructure model is necessary. A simple three-dimensional (3D) substructure commonly found in high integration Bipolar-CMOS-DMOS (BCD) technologies, is introduced for the assessment of thermo-mechanical phenomena. The investigated substructure is represented by a repetitive model with three signal metallisation lines. Numerical simulations based on finite element method (FEM) are performed to identify the areas of high stress accumulation and possible failure mechanisms. The structure is studied under two temperature variation conditions: 400-600 K and 300-650 K. Function of different electrical connectivity between metal layers, the displacement profile is analysed for identifying possible failure regions. First, an analysis of the mechanical displacement during one heating-cooling cycle is studied to understand the behaviour of the structure as response to the lateral temperature gradient. Further, the analysis is extended to a larger number of cycles to understand the plastic deformation accumulation over repeated cycling operation. Based on the displacement accumulation profiles, the possible failure positions and failure mechanisms are identified.