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Analog baseband chain with analog to digital converter (ADC) of Synthetic Aperture Radar (SAR) receiver

机译:模拟基带链与模拟到数字转换器(ADC)的合成孔径雷达(SAR)接收器

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An analog baseband chain together with an analog to digital converter (ADC) for a Synthetic Aperture Radar (SAR) receiver implemented in 130nm CMOS technology is presented in this paper. The baseband and the ADC are integrated on a single chip, occupying 1.6mm2 (I and Q branch) of active silicon area. The baseband is selectable between 50MHz and 160MHz bandwidth through switches and the voltage gain can be controlled between 22dB and 27dB. The ADC has selectable mode of 5, 6, 7 and 8 bits via control switches. The baseband and the ADC achieve measured spurious-free dynamic range more than 45dBc over the 160MHz band. The circuits, which use a 1.2V supply voltage, dissipates minimum power of 214mW with 50MHz baseband and 5 bit mode ADC, and maximum power of 344mW with 160MHz baseband and 8 bit mode ADC.
机译:本文提出了一种模拟基带链与用于合成孔径雷达(SAR)接收器的用于合成孔径雷达(SAR)接收器的模拟转换器(ADC)。基带和ADC集成在单个芯片上,占据有源硅区域的1.6mm 2 (i和q分支)。基带可在50MHz和160MHz带宽之间选择通过开关,电压增益可以控制在22dB和27dB之间。 ADC通过控制开关具有5,6,7和8位的可选模式。基带和ADC在160MHz波段上实现了超过45dBc的无杂散动态范围。使用1.2V电源电压的电路,使用50MHz基带和5位模式ADC耗散214MW的最小功率,以及具有160MHz基带和8位模式ADC的344MW的最大功率。

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