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Analog baseband chain with analog to digital converter (ADC) of Synthetic Aperture Radar (SAR) receiver

机译:具有合成孔径雷达(SAR)接收器的模数转换器(ADC)的模拟基带链

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An analog baseband chain together with an analog to digital converter (ADC) for a Synthetic Aperture Radar (SAR) receiver implemented in 130nm CMOS technology is presented in this paper. The baseband and the ADC are integrated on a single chip, occupying 1.6mm2 (I and Q branch) of active silicon area. The baseband is selectable between 50MHz and 160MHz bandwidth through switches and the voltage gain can be controlled between 22dB and 27dB. The ADC has selectable mode of 5, 6, 7 and 8 bits via control switches. The baseband and the ADC achieve measured spurious-free dynamic range more than 45dBc over the 160MHz band. The circuits, which use a 1.2V supply voltage, dissipates minimum power of 214mW with 50MHz baseband and 5 bit mode ADC, and maximum power of 344mW with 160MHz baseband and 8 bit mode ADC.
机译:本文介绍了采用130nm CMOS技术实现的合成孔径雷达(SAR)接收器的模拟基带链和模数转换器(ADC)。基带和ADC集成在单个芯片上,占有源硅面积的1.6mm 2 (I和Q分支)。基带可通过开关在50MHz至160MHz带宽之间选择,电压增益可控制在22dB至27dB之间。 ADC通过控制开关具有5、6、7和8位的可选模式。基带和ADC在160MHz频段上实现了超过45dBc的实测无杂散动态范围。这些电路使用1.2V电源电压,在50MHz基带和5位模式ADC的情况下,最小功耗为214mW,在160MHz基带和8位模式ADC的情况下,功耗为344mW。

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