Advances in Back-side Via Etching of SiC for GaN Device Applications

摘要

This paper will focus on the development of an 85μm diameter, 100μm deep SiC back-side via etch process for production. 100μm SiC/GaN wafers bonded to carriers were provided by WIN Semiconductors Corporation and etched at SPTS using an APS process module. Etch rates >1.3μm/min with cross-wafer uniformities of ＜±5% have been achieved along with selectivities to a patterned Ni hard mask in the range 30-40:1. A unique descum process has been introduced that reduces the defect level from up to 100% to <1%. Selectivities of >30:1 between the SiC and the GaN material have been obtained. Etch by-products are shown to be readily removed for compatibility with metallisation. Data is included on the etching of the GaN layer within the same process module. GaN etching is shown to be selective to the underlying Au metal and is compatible with end-point detection. Via resistances <6E-3Ω have been achieved.