integrated circuit interconnections; VLSI; transient analysis; integrated circuit modelling; high-speed integrated circuits; passive compact macromodeling; high-speed VLSI circuits; high-speed VLSI interconnects; circuit equations; high-frequency modules; passive model-reduction based algorithms; transient analysis; interconnect networks; efficient algorithm; computational cost reduction; passive reduction algorithms;
机译:神经网络在基于EM的VLSI高速电路互连仿真和优化中的应用
机译:通过延迟有理函数进行高速电路的紧凑宏建模
机译:混合时域宏建模和电路仿真,用于PCB上高速互连的信号完整性分析
机译:高速VLSI电路和互连的基于投影的快速被动紧凑宏建模
机译:用于高速电路的全局紧凑型无源宏建模算法。
机译:基于紧凑的高速图像的测量方法测量活组织的纵向运动
机译:具有嵌入式延迟的高速电路的被动宏观调