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International Conference on VLSI Design
International Conference on VLSI Design
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1.
Extracting exact finite state machines from behavioral SystemC descriptions
机译:
从行为系统描述中提取精确的有限状态机
作者:
Vikram Singh Saun
;
Preeti Ranjan Panda
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
C language;
finite state machines;
hardware description languages;
hardware-software codesign;
arbitrarily nested control structures;
behavioral SystemC descriptions;
behavioral synthesis;
cycle-by-cycle I/O behavior;
cycle-fixed mode;
finite state machines;
2.
Algorithmic implementation of low-power high performance FIR filtering IP cores
机译:
低功耗高性能冷冻滤波IP核的算法实现
作者:
Wang C.H.
;
Erdogan A.T.
;
Arslan T.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
FIR filters;
industrial property;
low-power electronics;
digital signal processing chips;
algorithmic implementation;
low-power FIR filter;
high performance FIR filter;
IP cores;
intellectual property cores;
coefficient segmentation;
combined segmentation algorithms;
block processing algorithms;
design methodology;
evaluation environment;
power consumption reduction;
3.
An effective VHDL-AMS simulation algorithm with event
机译:
具有事件的有效VHDL-AMS仿真算法
作者:
Ghasemi H.R.
;
Navabi Z.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
digital simulation;
hardware description languages;
mixed analogue-digital integrated circuits;
scheduling;
synchronisation;
VHDL-AMS language;
VHDL-AMS simulation algorithm;
analog simulation;
analog solver;
digital kernel;
digital simulation;
kernel synchronizati;
4.
Dictionary based code compression for variable length instruction encodings
机译:
基于字典的Dibessic字典可变长度指令编码
作者:
Das D.
;
Kumar R.
;
Chakrabarti P.P.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
reduced instruction set computing;
microprocessor chips;
instruction sets;
data compression;
encoding;
variable length instruction encoding;
machine code compression;
fixed length instruction encodings;
variable length instruction set processors;
RISC processor;
dictionary based code compression;
5.
SoC design methodology: a practical approach
机译:
SOC设计方法:一种实用的方法
作者:
Jain A.
;
Saha A.
;
Rao J.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
audio signal processing;
circuit complexity;
circuit layout;
design for testability;
digital signal processing chips;
formal verification;
high-speed integrated circuits;
integrated circuit design;
integrated circuit manufacture;
integrated circuit testing;
logic;
6.
Influence of leakage reduction techniques on delay/leakage uncertainty
机译:
泄漏减少技术对延迟/泄漏不确定性的影响
作者:
Yuh-Fang Tsai
;
Vijaykrishnan N.
;
Yuan Xie
;
Irwin M.J.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
Monte Carlo methods;
circuit optimisation;
delays;
integrated circuit design;
leakage currents;
low-power electronics;
Monte Carlo analysis;
body biasing;
delay/leakage uncertainty;
gate length;
integrated circuit design;
leakage power;
leakage reduction;
stack forci;
7.
Synthesis of reversible circuits for testing with universal test set and C-testability of reversible iterative logic arrays
机译:
具有可逆迭代逻辑阵列的通用测试集测试可逆电路的可逆电路
作者:
Chakraborty A.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
design for testability;
logic arrays;
logic testing;
logic gates;
fault simulation;
low-power electronics;
design for test;
fault models;
iterative logic arrays;
reversible circuits;
testability;
universal test sets;
low-power circuits;
quantum computation;
k-wire controlled NOT gates;
single stuck-at fault;
multiple stuck-at fault;
AND gate;
EXOR gate;
Reed-Muller circuits;
single cell fault;
8.
Evaluation of speed and area of clustered VLIW processors
机译:
聚类VLIW处理器速度和面积评估
作者:
Terechko A.
;
Garg M.
;
Corporaal H.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
microprocessor chips;
multiprocessing systems;
pipeline processing;
integrated circuit design;
clustered VLIW processors;
register file;
speculative analytical models;
VLIW datapath;
VLIW pipeline;
commercial media processor;
clock frequency;
FU bypass network;
clock speed;
9.
The impact of inductance on transients affecting gate oxide reliability
机译:
电感对影响栅极可靠性的瞬变的影响
作者:
Nagaraj N.S.
;
Hunter W.R.
;
Balsara P.
;
Cantrell C.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
inductance;
reliability theory;
semiconductor device reliability;
failure analysis;
fault simulation;
approximation theory;
transients;
inductance impact;
transients;
gate oxide reliability;
GOR failure rate;
voltage stress;
self-inductance;
parasitic inductance extraction;
inductance matrix;
modeling accuracy;
mathematical approximation;
inductance modeling theory;
10.
Variance reduction in Monte Carlo capacitance extraction
机译:
蒙特卡罗电容提取的差异减少
作者:
Batterywala S.H.
;
Desai M.P.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
Monte Carlo methods;
capacitance measurement;
random processes;
3D capacitance extraction;
Monte Carlo capacitance extraction;
conformal dielectrics;
dielectric layers;
error bounds;
importance sampling;
random walk;
statistical capacitance estimation;
stratified s;
11.
Embedded Tutorial Revisiting VLSI Interconnects in Deep Sub-Micron: Some Open Questions
机译:
嵌入式教程重新审视Deep Sub-Micron中的VLSI互连:一些打开的问题
作者:
Parthasarathi Dasgupta
会议名称:
《International Conference on VLSI Design》
|
2005年
12.
An effective VHDL-AMS simulation algorithm with event
机译:
具有事件的有效VHDL-AMS仿真算法
作者:
Ghasemi H.R.
;
Navabi Z.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
digital simulation;
hardware description languages;
mixed analogue-digital integrated circuits;
scheduling;
synchronisation;
VHDL-AMS simulation algorithm;
VHDL-AMS language;
mixed signal circuits;
analog simulation;
digital simulation;
simulation kernels;
kernel synchronization;
analog solver;
digital kernel;
simulator;
scheduling algorithm;
synchronization algorithm;
13.
A novel approach to minimizing reconfiguration cost for LUT-based FPGAs
机译:
一种最小化基于LUT的FPGA的重新配置成本的新方法
作者:
Prasad Raghuraman K.
;
Haibo Wang
;
Tragoudas S.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
circuit optimisation;
field programmable gate arrays;
logic CAD;
reconfigurable architectures;
table lookup;
LUT-based FPGA;
Xilinx Virtex FPGA;
heuristic procedure;
input orders;
logic function;
look up table;
memory locations;
partial reconfiguration;
polynomial ti;
14.
A wide-swing V/sub T/-referenced circuit with insensitivity to device mismatch
机译:
一个宽v / sub t / -referenced电路,具有设备不匹配的不敏感
作者:
Chih-Jen Yen
;
Wen-Yaw Chung
;
Mely Chen Chi
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
CMOS analogue integrated circuits;
bipolar transistors;
reference circuits;
CMOS technology;
PNP structure;
bias current;
bipolar-junction transistors;
current matching;
device mismatch;
error current;
p-substrate;
voltage-signal swings;
wide-swing V/sub T/ referenc;
15.
Using contrapositive law in an implication graph
机译:
在蕴涵图中使用矛盾法
作者:
Dave K.K.
;
Agrawal V.D.
;
Bushnell M.L.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
digital circuits;
fault location;
graph theory;
redundancy;
anding node;
benchmark circuit c1908;
contrapositive law;
digital circuits synthesis;
digital circuits verification;
graph edge;
implication graph;
n-input gate;
oring node structure;
partial implications;
re;
16.
Computer aided test (CAT) tool for mixed signal SOCs
机译:
混合信号SOC的计算机辅助测试(CAT)工具
作者:
Banerjee S.
;
Mukhopadhyay D.
;
Chowdhury D.R.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
mixed analogue-digital integrated circuits;
circuit CAD;
system-on-chip;
design for testability;
scheduling;
integrated circuit testing;
computer aided test;
CAT tool;
mixed signal SOC;
SOC design;
DFT solution;
digital testing;
scheduling algorithm;
switches;
ISCAS'89 circuits;
digital core;
ITC '97 circuits;
analog core;
17.
Testing nanometer digital integrated circuits: myths, reality and the road ahead
机译:
测试纳米数字集成电路:神话,现实和前方的道路
作者:
Blanton S.
;
Mitra S.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
integrated circuit testing;
built-in self test;
nanoelectronics;
logic testing;
integrated circuit yield;
fault diagnosis;
nanometer digital integrated circuit testing;
high-test quality;
nanometer technology;
test compression;
defect diagnosis;
magnitude improvement;
test cost reduction;
built-in-self-test features;
manufacturing processes;
18.
Modeling usable reusable transactors in system Verilog
机译:
系统Verilog中的建模可用和可重复使用的交易者
作者:
Bergeron J.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
hardware description languages;
transaction processing;
formal verification;
object-oriented methods;
application program interfaces;
usable transactors;
reusable transactor models;
system Verilog;
device under test;
object-oriented approach;
callback methods;
transactor functionality;
design under verification;
object-oriented features;
procedural programming model;
transactor modeling problem;
constrained-random verification;
19.
A novel low power 16/spl times/16 content addressable memory using PAL
机译:
使用PAL的新型低功率16 / SPL时间/ 16内容可寻址存储器
作者:
Bala G.J.
;
Perinbam J.R.P.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
SPICE;
content-addressable storage;
logic design;
low-power electronics;
0.6 micron;
10 MHz;
CAM;
CMOS technology;
PAL;
SPICE simulation;
circuit design;
compare operation;
content addressable memory;
pass transistor adiabatic logic;
power saving;
read operation;
write;
20.
Multivariate normal distribution based statistical timing analysis using global projection and local expansion
机译:
基于多变量的正态分布基于全局投影和本地扩展的统计时序分析
作者:
Baohua Wang
;
Mazumder P.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
integrated circuit design;
network analysis;
normal distribution;
statistical analysis;
delays;
multivariate normal distribution;
statistical timing analysis;
global projection;
local expansion;
delay correlations;
arrival time correlations;
re-convergent paths;
maximum circuit delay;
21.
Extracting exact finite state machines from behavioral SystemC descriptions
机译:
从行为系统描述中提取精确的有限状态机
作者:
Vikram Singh Saun
;
Preeti Ranjan Panda
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
finite state machines;
hardware-software codesign;
hardware description languages;
C language;
finite state machines;
behavioral SystemC descriptions;
cycle-by-cycle I/O behavior;
behavioral synthesis;
cycle-fixed mode;
arbitrarily nested control structures;
22.
ADOPT: an approach to activity based delay optimization
机译:
采用:基于活动的延迟优化方法
作者:
Arora G.
;
Sharma A.
;
Nagchoudhury D.
;
Balaknshnan M.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
circuit optimisation;
delays;
logic design;
thermal management (packaging);
ADOPT;
activity based delay optimization;
chip area;
critical path;
device temperatures;
gate selective replacement;
hotspot intersection;
shrinking devices;
switching activity;
23.
A Wide-Swing V{sub}T-Referenced Circuit with Insensitivity to Device Mismatch
机译:
宽v {sub} t引用电路,具有设备不匹配的不敏感性
作者:
Chih-Jen Yen
;
Wen-Yaw Chung
;
Mely Chen Chi
会议名称:
《International Conference on VLSI Design》
|
2005年
24.
An accurate energy and thermal model for global signal buses
机译:
全局信号总线的精确能量和热模型
作者:
Sundaresan K.
;
Mahapatra N.R.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
integrated circuit interconnections;
integrated circuit reliability;
integrated circuit modelling;
dielectric materials;
crosstalk;
VLSI;
system buses;
global signal buses;
thermal effects;
reliability characteristics;
performance characteristics;
packaging requirements;
fabrication technologies;
low-K dielectrics;
intermetal dielectrics;
interlayer dielectrics;
RC delay reduction;
dynamic power dissipation;
crosstalk;
bus lines;
dynamic simulation;
bus energy dissipation;
real-world address traces;
temperature rise;
instruction buses;
data address buses;
SPEC CPU2000 benchmark programs;
32 bit;
25.
A low overhead high speed histogram based test methodology for analog circuits and IP cores
机译:
基于低开销高速直方图的模拟电路和IP核的测试方法
作者:
Bahukudumbi S.
;
Bharath K.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
analogue circuits;
circuit testing;
histogram test methodology;
analog circuit testing;
IP cores;
histogram-correlation technique;
core test wrapper;
continuous-time state-variable filter;
fault free correlation values;
26.
Design, testing, and applications of digital microfluidics-based biochips
机译:
基于数字微流体的Biochips的设计,测试和应用
作者:
Chakrabarty K.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
biomolecular electronics;
fault simulation;
microfluidics;
reliability;
automated drug discovery;
availability;
catastrophic fault testing;
diagnostic procedure;
digital microfluidics technology;
digital microfluidics-based biochips;
embedded tutorial;
fault models;
27.
Modeling usable reusable transactors in system Verilog
机译:
系统Verilog中的建模可用和可重复使用的交易者
作者:
Bergeron J.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
application program interfaces;
formal verification;
hardware description languages;
object-oriented methods;
transaction processing;
callback methods;
constrained-random verification;
design under verification;
device under test;
object-oriented approach;
object-;
28.
Testing nanometer digital integrated circuits: myths, reality and the road ahead
机译:
测试纳米数字集成电路:神话,现实和前方的道路
作者:
Blanton S.
;
Mitra S.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
built-in self test;
fault diagnosis;
integrated circuit testing;
integrated circuit yield;
logic testing;
nanoelectronics;
built-in-self-test features;
defect diagnosis;
high-test quality;
magnitude improvement;
manufacturing processes;
nanometer digital integrated;
29.
A nanosensor array-based VLSI gas discriminator
机译:
基于纳米传感器阵列的VLSI气体鉴别器
作者:
Irick K.M.
;
Xu W.
;
Vijaykrishnan N.
;
Irwin M.J.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
gas sensors;
nanowires;
VLSI;
pattern classification;
chemioception;
nanosensor array;
VLSI gas discriminator;
chemiresistive nanowires;
cross-reactive sensor arrays;
human olfactory system;
pattern classifier;
30.
A wide-swing V/sub T/-referenced circuit with insensitivity to device mismatch
机译:
一个宽v / sub t / -referenced电路,具有设备不匹配的不敏感
作者:
Chih-Jen Yen
;
Wen-Yaw Chung
;
Mely Chen Chi
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
reference circuits;
CMOS analogue integrated circuits;
bipolar transistors;
device mismatch;
wide-swing V/sub T/ referenced circuit;
CMOS technology;
wide-swing cascode design;
voltage-signal swings;
current matching;
error current;
bipolar-junction transistors;
p-substrate;
PNP structure;
bias current;
31.
A 10-bit 80-MSPS 2.5-V 27.65-mW 0.185-mm/sup 2/ segmented current steering CMOS DAC
机译:
10位80-MSPS 2.5-V 27.65-MW 0.185-mm / sup 2 /分段电流转向CMOS DAC
作者:
Haider S.
;
Banerjee S.
;
Ghosh A.
;
Ravi sankar Prasad
;
Chatterjee A.
;
Kumar Dey S.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
digital-analogue conversion;
CMOS analogue integrated circuits;
mixed analogue-digital integrated circuits;
low-power electronics;
segmented current steering CMOS DAC;
digital-to-analog converter;
double poly four metal CMOS technology;
mixed-signal applications;
differential nonlinearity;
integral nonlinearity;
MOS analog circuits;
mixed analog-digital integrated circuits;
low-power electronics;
2.5 V;
27.65 mW;
0.25 micron;
10 bits;
32.
Q-PREZ: QBF evaluation using partition, resolution and elimination with ZBDDs
机译:
Q-PREZ:使用ZBDDS使用分区,分辨率和消除QBF评估
作者:
Chandrasekar K.
;
Hsiao M.S.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
Boolean functions;
binary decision diagrams;
decision trees;
data structures;
logic CAD;
VLSI;
Q-PREZ;
quantified Boolean formula;
VLSI CAD problems;
resolution-based methods;
space explosion;
QBF solvers;
decision tree search;
Davis-Putnam Logemann and Loveland procedure;
data structures;
CNF;
zero-suppressed binary decision diagrams;
33.
Heterogeneous and multi-level compression techniques for test volume reduction in systems-on-chip
机译:
用于测试系统的测试体积减少的异质和多级压缩技术
作者:
Linggapan L.
;
Ravi S.
;
Raghunathan A.
;
Jha N.K.
;
Chakradhar S.T.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
data compression;
system-on-chip;
integrated circuit testing;
logic testing;
automatic test pattern generation;
instruction sets;
data reduction;
heterogeneous compression;
multilevel compression;
systems-on-chip;
test compression;
low hardware overhead;
low decompression time;
architectural customization;
decompression functionality partitioning;
hardware overhead reduction;
industrial media processing SoC;
test data volume reduction;
34.
Charge-recovery power clock generators for adiabatic logic circuits
机译:
绝热逻辑电路的充电恢复功率时钟发生器
作者:
Arsalan M.
;
Shams M.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
CMOS logic circuits;
circuit simulation;
clocks;
logic circuits;
0.18 micron;
CMOS technology;
adiabatic logic circuits;
charge recovery;
energy efficiency;
post layout simulations;
power clock generators;
35.
The impact of inductance on transients affecting gate oxide reliability
机译:
电感对影响栅极可靠性的瞬变的影响
作者:
Nagaraj N.S.
;
Hunter W.R.
;
Balsara P.
;
Cantrell C.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
approximation theory;
failure analysis;
fault simulation;
inductance;
reliability theory;
semiconductor device reliability;
transients;
GOR failure rate;
gate oxide reliability;
inductance impact;
inductance matrix;
inductance modeling theory;
mathematical approxima;
36.
Variable resizing for area improvement in behavioral synthesis
机译:
变量调整为行为合成区域改善的大小
作者:
Gopalakrishnan R.
;
Moona R.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
high level synthesis;
C language;
C++ language;
variable resizing;
area improvement;
behavioral synthesis;
high level synthesis tools;
algorithmic description;
register transfer language description;
C language;
C++ language;
hardware specification language;
VHDL;
Verilog;
combinatorial area;
noncombinatorial area;
37.
Off-line testing of asynchronous circuits
机译:
异步电路的离线测试
作者:
Koppad D.
;
Bystrov A.
;
Yakovlev A.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
asynchronous circuits;
circuit testing;
Petri nets;
fault diagnosis;
offline testing;
asynchronous circuits;
circuit testing;
direct mapping;
I-safe Petri nets;
physical faults;
high-level specification;
pseudo clock;
hazard handling;
fault activation;
stuck-at-faults;
testability feature;
test sequences;
38.
Crosstalk noise analysis at multiple frequencies
机译:
多个频率下串扰噪声分析
作者:
Shrivastava S.
;
Chandrasekar S.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
clocks;
crosstalk;
integrated circuit design;
integrated circuit noise;
system-on-chip;
SOC designs;
clock frequency;
crosstalk noise analysis;
glitch propagation effects;
switching aggressors;
switching overlap;
39.
65nm ombudsman
机译:
65nm监察员
作者:
Vucurevich T.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
VLSI;
nanoelectronics;
integrated circuit design;
integrated circuit manufacture;
VLSI design;
65nm ombudsman;
semiconductor industry;
design process;
manufacturing process;
power density;
process variability;
65 nm;
40.
Automatic device layout generation for analog layout retargeting
机译:
模拟布局重新标准的自动设备布局生成
作者:
Hartono R.
;
Jangkrajarng N.
;
Bhattacharya S.
;
Richard Shi C.J.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
analogue integrated circuits;
circuit layout CAD;
integrated circuit layout;
active device optimization;
analog integrated circuits;
analog layout retargeting;
automatic design reuse methodology;
automatic device layout generation;
design-space exploration engin;
41.
High-speed interconnect technology: on-chip and off-chip
机译:
高速互连技术:片上和片外
作者:
Sapatnekar S.
;
Roychowdhury J.
;
Harjani R.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
integrated circuit interconnections;
system-on-chip;
high-speed integrated circuits;
delays;
circuit optimisation;
integrated circuit design;
logic design;
crosstalk;
transceivers;
driver circuits;
signalling;
clocks;
phase noise;
jitter;
high-speed interconnect technology;
on-chip interconnect delays;
on-chip RC delay;
on-chip RLC delay;
on-chip interconnect technology;
off-chip interconnect technology;
on-chip wire modeling;
delay calculations;
optimization techniques;
design techniques;
cross-talk modeling;
high-speed I-O transceivers;
high-speed drivers;
binary signaling;
multilevel signaling;
clock circuits;
data recovery circuits;
jitter modeling;
phase noise modeling;
42.
An ultra-fast, on-chip BiST for RF low noise amplifiers
机译:
用于RF低噪声放大器的超快速,片上BIST
作者:
Gopalan A.
;
Das T.
;
Washburn C.
;
Mukund P.R.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
built-in self test;
integrated circuit testing;
radiofrequency amplifiers;
radiofrequency integrated circuits;
0.25 micron;
1.9 GHz;
DSP cores;
IBM 6RF process;
RF low noise amplifiers;
built in self test;
functional specifications;
self test time;
43.
Revisiting VLSI interconnects in deep sub-micron: some open questions
机译:
重新审视Deep Sim-Micron中的VLSI互连:一些打开的问题
作者:
Dasgupta P.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
VLSI;
circuit complexity;
delay estimation;
integrated circuit design;
integrated circuit interconnections;
integrated circuit measurement;
network routing;
VLSI circuits;
VLSI interconnects;
deep submicron technology;
delay estimators;
des;
44.
Crosstalk noise analysis at multiple frequencies
机译:
多个频率下串扰噪声分析
作者:
Shrivastava S.
;
Chandrasekar S.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
system-on-chip;
integrated circuit design;
crosstalk;
integrated circuit noise;
clocks;
crosstalk noise analysis;
SOC designs;
switching aggressors;
clock frequency;
switching overlap;
glitch propagation effects;
45.
Dynamically exploiting frequent operand values for energy efficiency in integer functional units
机译:
在整数功能单元中动态利用频繁操作数值的能效
作者:
Gandhi K.R.
;
Mahapatra N.R.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
circuit optimisation;
circuit simulation;
integrated circuit design;
SPEC CPU2000 benchmarks;
area overheads;
circuit-level simulations;
disjoint operand subwords;
energy efficiency;
energy model;
energy optimization;
energy-optimal partitioning algorithm;
exploita;
46.
Architectural, system level and protocol level techniques for power optimization for networked embedded systems
机译:
网络嵌入式系统电力优化的架构,系统级和协议级技术
作者:
Benini L.
;
Shuklam SK
;
Gupta R.K.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
circuit optimisation;
computer architecture;
embedded systems;
minimisation;
power consumption;
protocols;
system-on-chip;
application specific techniques;
architectural level power optimization;
clock gating;
dynamic power management;
multimedia hardware systems;
n;
47.
The high walls have crumpled system-on-a-chip technology
机译:
高墙弄皱了系统 - 芯片技术
作者:
Liu C.L.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
VLSI;
integrated circuit technology;
system-on-chip;
keynote address;
system-on-a-chip technology;
48.
A methodology and tooling enabling application specific processor design
机译:
一种方法和工具,可实现特定于应用程序设计
作者:
Hoffmann A.
;
Fiedler F.
;
Nohl A.
;
Parupalli S.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
application specific integrated circuits;
circuit simulation;
fast Fourier transforms;
hardware description languages;
hardware-software codesign;
integrated circuit design;
microprocessor chips;
LISA 2.0 language;
SIMD;
VLIW;
application specific instruction set;
49.
A novel approach to minimizing reconfiguration cost for LUT-based FPGAs
机译:
一种最小化基于LUT的FPGA的重新配置成本的新方法
作者:
Prasad Raghuraman K.
;
Haibo Wang
;
Tragoudas S.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
field programmable gate arrays;
circuit optimisation;
reconfigurable architectures;
table lookup;
logic CAD;
reconfiguration cost minimization;
LUT-based FPGA;
reconfiguration bits;
input orders;
memory locations;
partial reconfiguration;
problem formulation;
logic function;
heuristic procedure;
polynomial time;
Xilinx Virtex FPGA;
size reduction;
reconfiguration bitstreams;
look up table;
50.
A reconfigurable oscillator topology for dual-band operation
机译:
用于双频操作的可重构振荡器拓扑
作者:
Tien-Ling Hsieh
;
Ranjit Gharpurey
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
oscillators;
MOS integrated circuits;
network topology;
integrated circuit design;
reconfigurable oscillator topology;
dual-band operation;
area-efficient oscillator topology;
oscillation frequencies;
frequency divider;
area requirements;
power requirements;
phase noise performance;
single-band NMOS cross-coupled oscillator;
51.
Dynamically exploiting frequent operand values for energy efficiency in integer functional units
机译:
在整数功能单元中动态利用频繁操作数值的能效
作者:
Gandhi K.R.
;
Mahapatra N.R.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
integrated circuit design;
circuit simulation;
circuit optimisation;
frequent operand values;
energy efficiency;
integer functional units;
operand subword;
disjoint operand subwords;
exploitable subword value combination;
energy optimization;
hardware topology;
energy-optimal partitioning algorithm;
energy model;
circuit-level simulations;
SPEC CPU2000 benchmarks;
area overheads;
52.
Power variability and its impact on design
机译:
功率变异性及其对设计的影响
作者:
Devgan A.
;
Nassif S.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
integrated circuit design;
leakage currents;
microprocessor chips;
power consumption;
handheld device;
integrated circuit design;
leakage power;
power consumption;
power variability;
process technologies;
process variations;
server microprocessors;
53.
A fast buffered routing tree construction algorithm under accurate delay model
机译:
准确延迟模型的快速缓冲路由树施工算法
作者:
Yibo Wang
;
Yici Cai
;
Xianlong Hong
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
circuit optimisation;
VLSI;
buffer circuits;
integrated circuit interconnections;
trees (mathematics);
delays;
routing tree construction algorithm;
buffer insertion method;
VLSI design;
buffer delays;
delay estimation errors;
power supply;
interconnect delay optimization;
accurate delay model;
buffer/wire sizing;
routing obstacles;
total buffer area reduction;
Fast-RTBW algorithm;
obstacle-aware routing;
54.
Optimization of mixed logic circuits with application to a 64-bit static adder
机译:
应用于64位静态加法器的混合逻辑电路优化
作者:
Yuanzhong Wan
;
Shams M.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
CMOS logic circuits;
adders;
circuit optimisation;
delays;
logic design;
0.18 micron;
64 bits;
650 ps;
CMOS logic delay optimization;
CPL chain;
TSMC technology;
buffer insertion;
mixed logic circuits;
pass transistors;
static adder;
55.
Power monitors: a framework for system-level power estimation using heterogeneous power models
机译:
电力监视器:使用异构电源模型的系统级功率估计框架
作者:
Bansal N.
;
Lahiri K.
;
Raghunathan A.
;
Chakradhar S.T.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
circuit optimisation;
circuit simulation;
integrated circuit modelling;
low-power electronics;
power consumption;
power measurement;
system-on-chip;
component power models;
component-level execution;
design cycle;
extensive design space exploration;
heterogeneous p;
56.
Programmable high frequency RC oscillator
机译:
可编程高频RC振荡器
作者:
Bala F.
;
Nandy T.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
RC circuits;
low-power electronics;
microwave oscillators;
programmable circuits;
voltage-controlled oscillators;
0.18 micron;
RC oscillator;
RC time-constant;
VCO frequency;
calibration interval;
capacitors;
digital codes;
low voltage operation;
programmable high fr;
57.
Distance restricted scan chain reordering to enhance delay fault coverage
机译:
距离限制扫描链重新排序以增强延迟故障覆盖
作者:
Wei Li
;
Seongmoon Wang
;
Chakradhar S.T.
;
Reddy S.M.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
boundary scan testing;
delays;
fault simulation;
flip-flops;
logic testing;
ISCAS 89 circuits;
delay fault coverage;
distance restricted scan chain reordering;
distance restriction;
flip flops;
local layout modifications;
routing overhead;
stuck-open faults;
test pat;
58.
A principal component neural network-based face recognition system and ASIC implementation
机译:
基于主组分的基于神经网络的面部识别系统和ASIC实现
作者:
Chakka Siva Sai Prasanna
;
Sudha N.
;
Kamakoti V.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
application specific integrated circuits;
computer vision;
face recognition;
neural net architecture;
principal component analysis;
ASIC implementation;
PCA;
PCNN;
computer-aided vision;
digital hardware design;
directional lighting;
face recognition system;
hardwar;
59.
Revisiting VLSI interconnects in deep sub-micron: some open questions
机译:
重新审视Deep Sim-Micron中的VLSI互连:一些打开的问题
作者:
Dasgupta P.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
integrated circuit design;
integrated circuit interconnections;
delay estimation;
integrated circuit measurement;
circuit complexity;
VLSI;
network routing;
CMOS integrated circuits;
VLSI interconnects;
deep submicron technology;
design complexity;
VLSI circuits;
routers design;
design convergence;
delay estimators;
global routing trees;
interconnect performance measurement;
60.
A 160 MSPS 8-bit pipeline based ADC
机译:
基于ADC的160 MSPS 8位管道
作者:
Haider S.
;
Ghosh A.
;
Ravi sankar Prasad
;
Anirban Chatierjeee
;
Swapna Banerjee
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
BiCMOS integrated circuits;
analogue-digital conversion;
comparators (circuits);
pipeline processing;
sample and hold circuits;
135 mW;
3.3 V;
8 bits;
analog power supply;
comparator;
double poly BiCMOS technology;
double sampling sample-and-hold;
multiplying digita;
61.
Formal methods for analyzing the completeness of an assertion suite against a high-level fault model
机译:
用于分析断言套件对高级故障模型的完整性的正式方法
作者:
Sayanlan Das
;
Ansuman Banerjee
;
Prasenjit Basu
;
Pallab Dasgupta
;
Chakrabarti P.P.
;
Chunduri Rama Mohan
;
Fix L.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
program verification;
formal specification;
computational complexity;
formal methods;
assertion suite completeness;
fault model;
formal property verification;
formal specification;
coverage analysis;
behavioral gaps;
62.
Implementing LDPC decoding on network-on-chip
机译:
在片上实施LDPC解码
作者:
Theocharides T.
;
Link G.
;
Vijaykrishnan N.
;
Irwin M.J.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
parity check codes;
error correction codes;
computational complexity;
iterative decoding;
message passing;
graph theory;
low-density parity check codes;
disk drives;
Shannon-limit communication channel capacity;
message-passing bipartite graph;
code rate;
1.2 Gbit/s;
63.
Battery model for embedded systems
机译:
嵌入式系统电池型号
作者:
Rao V.
;
Singhal G.
;
Kumar A.
;
Navet N.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
embedded systems;
secondary cells;
battery lifetime;
battery model;
battery recovery behavior;
discharge profiles;
embedded systems;
rate capacity effect;
stochastic model;
64.
A RISC hardware platform for low power Java
机译:
用于低功耗Java的RISC硬件平台
作者:
Capewell P.
;
Watson I.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
Java;
embedded systems;
reduced instruction set computing;
Java;
RISC hardware platform;
RISC processor;
asynchronous implementation;
binary format;
embedded systems;
execution speed;
gate level simulation;
hardware support;
memory reduction;
power requirements reduc;
65.
Synthesis of majority and minority networks and its applications to QCA, TPL and SET based nanotechnologies
机译:
综合多数和少数民族网络及其对QCA,TPL和基于纳米技术的应用
作者:
Rui Zhang
;
Gupta P.
;
Jha N.K.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
network synthesis;
Boolean functions;
cellular automata;
tunnelling;
nanotechnology;
majority/minority network synthesis;
QCA;
TPL;
nanotechnology;
Boolean functions;
nanoscale technology;
quantum cellular automata;
tunneling phase logic;
single electron tunneling;
minority logic;
automation tool;
majority logic synthesizer;
Boolean logic synthesis tool;
AND/OR gates;
majority gates;
66.
Optimization of mixed logic circuits with application to a 64-bit static adder
机译:
应用于64位静态加法器的混合逻辑电路优化
作者:
Yuanzhong Wan
;
Shams M.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
CMOS logic circuits;
logic design;
adders;
circuit optimisation;
delays;
mixed logic circuits;
static adder;
CMOS logic delay optimization;
pass transistors;
buffer insertion;
CPL chain;
TSMC technology;
0.18 micron;
64 bits;
650 ps;
67.
A framework for distributed and hierarchical design-for-test
机译:
分布式和分层设计的框架框架
作者:
Ravikumar C.P.
;
Dandamudi R.
;
Devanathan V.R.
;
Haldar N.
;
Kiran K.
;
Kumar V.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
automatic test pattern generation;
built-in self test;
design for testability;
integrated circuit testing;
IDDQ tests;
burn-in tests;
delay tests;
design cycle time;
distributed computing;
distributed design for test;
hierarchical design for test;
logic BIST patter;
68.
Synthesis of application-specific heterogeneous multiprocessor architectures using extensible processors
机译:
使用可扩展处理器综合应用程序特定的异构多处理器架构
作者:
Fei Sun
;
Jha N.K.
;
Ravi S.
;
Raghunathan A.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
microprocessor chips;
system-on-chip;
instruction sets;
integrated circuit design;
hardware-software codesign;
embedded systems;
application-specific heterogeneous multiprocessor architecture;
extensible processors;
nanometer fabrication;
multiple processors;
heterogeneous multiprocessor systems-on-chip;
power consumption;
instruction set;
custom instruction selection;
task assignment;
task scheduling;
synthesized multiprocessor architecture;
iterative improvement algorithm;
task-level software pipelining;
heterogeneous multiprocessor synthesis;
Xtensa;
Tensilica Inc.;
software benchmarks;
symmetric multiprocessor architectures;
69.
Projection based fast passive compact macromodeling of high-speed VLSI circuits and interconnects
机译:
基于投影的高速VLSI电路和互连的快速被动紧凑型大规模
作者:
Saraswat D.
;
Achar R.
;
Nakhla M.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
integrated circuit interconnections;
VLSI;
transient analysis;
integrated circuit modelling;
high-speed integrated circuits;
passive compact macromodeling;
high-speed VLSI circuits;
high-speed VLSI interconnects;
circuit equations;
high-frequency modules;
passive model-reduction based algorithms;
transient analysis;
interconnect networks;
efficient algorithm;
computational cost reduction;
passive reduction algorithms;
70.
A principal component neural network-based face recognition system and ASIC implementation
机译:
基于主组分的基于神经网络的面部识别系统和ASIC实现
作者:
Chakka Siva Sai Prasanna
;
Sudha N.
;
Kamakoti V.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
face recognition;
principal component analysis;
neural net architecture;
application specific integrated circuits;
computer vision;
principal component neural network;
face recognition system;
ASIC implementation;
principal component analysis;
PCA;
computer-aided vision;
PCNN;
directional lighting;
digital hardware design;
hardware-based recognition;
71.
Q-PREZ: QBF evaluation using partition, resolution and elimination with ZBDDs
机译:
Q-PREZ:使用ZBDDS使用分区,分辨率和消除QBF评估
作者:
Chandrasekar K.
;
Hsiao M.S.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
Boolean functions;
VLSI;
binary decision diagrams;
data structures;
decision trees;
logic CAD;
CNF;
Davis-Putnam Logemann and Loveland procedure;
Q-PREZ;
QBF solvers;
VLSI CAD problems;
data structures;
decision tree search;
quantified Boolean formula;
resolution-base;
72.
An active learning scheme using support vector machines for analog circuit feasibility classification
机译:
用于模拟电路可行性分类的支持向量机的主动学习方案
作者:
Ding M.
;
Vemur R.I.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
analogue circuits;
integrated circuit design;
integrated circuit modelling;
learning (artificial intelligence);
support vector machines;
circuit CAD;
active learning scheme;
support vector machines;
analog circuit feasibility classification;
feasibility design space;
accuracy metrics;
passive learning scheme;
73.
Estimation of switching activity in sequential circuits using dynamic Bayesian networks
机译:
动态贝叶斯网络估算顺序电路切换活动
作者:
Bhanja S.
;
Lingasubramanian K.
;
Ranganathan N.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
belief networks;
inference mechanisms;
integrated circuit modelling;
probability;
sequential circuits;
sequential switching;
switching circuits;
IS-CAS'89;
benchmark circuits;
computational mechanism;
dynamic Bayesian network;
dynamic Bayesian networks;
exact model;
74.
A verification system for transient response of analog circuits using model checking
机译:
模型检查的模拟电路瞬态响应验证系统
作者:
Tathagato Rai Dastidar
;
Chakrabarti P.P.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
SPICE;
analogue integrated circuits;
constraint handling;
finite state machines;
formal verification;
program debugging;
query processing;
temporal logic;
transient response;
Ana CTL;
SPICE simulations;
analog circuit verification;
conventional temporal logics;
desig;
75.
A new asymmetric skewed buffer design for runtime leakage power reduction
机译:
一种新的不对称偏斜缓冲器设计,用于运行时漏功率降低
作者:
Yu-Shiang Lin
;
Sylvester D.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
CMOS memory circuits;
buffer storage;
invertors;
leakage currents;
transistors;
0.13 micron;
CMOS noninverting buffer;
NMOS;
PMOS;
asymmetric skewed buffer design;
dynamic power dissipation;
high-Vt devices;
inverters;
propagation delay;
runti;
76.
Behavioral synthesis of data-dominated circuits for minimal energy implementation
机译:
用于最小能量实现的数据主导电路的行为综合
作者:
Xiaoyong Tang
;
Tianyi Jiang
;
Jones A.
;
Banerjee P.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
circuit optimisation;
high level synthesis;
integer programming;
integrated circuit design;
linear programming;
low-power electronics;
behavioral synthesis;
data-dominated circuits;
integer linear programming model;
module binding;
module scheduling;
module selecti;
77.
Algorithmic implementation of low-power high performance FIR filtering IP cores
机译:
低功耗高性能冷冻滤波IP核的算法实现
作者:
Wang C.H.
;
Erdogan A.T.
;
Arslan T.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
FIR filters;
digital signal processing chips;
industrial property;
low-power electronics;
IP cores;
algorithmic implementation;
block processing algorithms;
coefficient segmentation;
combined segmentation algorithms;
design methodology;
evaluation environment;
high;
78.
Efficient space/time compression to reduce test data volume and testing time for IP cores
机译:
有效的空间/时间压缩,以减少IP核的测试数据量和测试时间
作者:
Lei Li
;
Chakrabarty K.
;
Kajihara S.
;
Swaminathan S.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
circuit testing;
logic testing;
boundary scan testing;
data compression;
automatic test pattern generation;
data reduction;
industrial property;
test data volume reduction;
IP core testing;
2D space-time compression;
test application time reduction;
scan testing;
intellectual property cores;
scan chain compatibility;
logic dependencies;
single-level decompression circuit;
two-input gates;
width compression;
test patterns;
c tester channels;
height compression;
fan-out structure;
tester-driven external scan pins;
internal scan chains;
industrial circuits;
79.
Power switch network design for MTCMOS
机译:
MTCMOS电源开关网络设计
作者:
Vilangudipitchai R.
;
Balsara P.T.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
leakage currents;
transistors;
threshold logic;
distributed shared memory systems;
automatic test pattern generation;
capacitance;
logic CAD;
power switch network design;
MTCMOS;
multithreshold CMOS;
leakage power reduction;
DSM design;
cluster sleep transistor design;
sleep transistor clustering;
chip decoupling capacitance;
sleep transistor area reduction;
leakage current reduction;
gate clustering;
ATPG vectors;
DASTD;
80.
Design of a reversible binary coded decimal adder by using reversible 4-bit parallel adder
机译:
使用可逆的4位并行加法器设计可逆二进制编码的小数加法器
作者:
Babu H.M.H.
;
Chowdhury A.R.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
adders;
binary codes;
error correction codes;
logic design;
logic gates;
BCD number;
binary variables;
error correcting modules;
reversible 4-bit parallel adder;
reversible binary coded decimal adder;
81.
Lithography driven layout design
机译:
光刻驱动布局设计
作者:
Garg M.
;
Le Cam L.
;
Gonzalez M.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
integrated circuit layout;
nanolithography;
circuit complexity;
circuit optimisation;
CMOS integrated circuits;
lithography driven layout design;
layout optimisation;
lithographic complexity;
IC technologies;
IC layouts;
manufacturability rules;
mask cost;
litho tools;
CMOS technology;
litho printability;
65 nm;
82.
Dual-edge triggered static pulsed flip-flops
机译:
双边缘触发静态脉冲触发器
作者:
Aliakbar Ghadiri
;
Hamid Mahmoodi
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
flip-flops;
pulse generators;
power consumption;
SPICE;
low-power electronics;
clocks;
dual-edge triggered static pulsed flip-flops;
low-power DSPFF;
dual-edge pulse generator;
static flip-flop;
toggling delays;
internal node transitions;
power consumption reduction;
double-edge triggering;
power dissipation;
clock distribution networks;
HSPICE simulation;
PDP reduction;
hybrid-latch flip-flop;
conditional-capture flip-flop;
400 MHz;
83.
An efficient methodology for noise characterization
机译:
一种有效的噪声表征方法
作者:
Varshney G.K.
;
Chandrasekar S.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
application specific integrated circuits;
circuit simulation;
curve fitting;
integrated circuit design;
integrated circuit noise;
interpolation;
noise measurement;
ASIC cell libraries;
capacitive coupling;
chip level analysis;
nanometer process technology;
noise ch;
84.
ISIS: a genetic algorithm based technique for custom on-chip interconnection network synthesis
机译:
ISIS:一种基于遗传算法的芯片互联网络合成技术
作者:
Srinivasan K.
;
Chatha K.S.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
system-on-chip;
genetic algorithms;
power consumption;
packet switching;
circuit optimisation;
integrated circuit interconnections;
ISIS;
genetic algorithm;
custom on-chip interconnection;
network synthesis;
on-chip packet switched interconnection networks;
network-on-chip;
system-on-chip design;
power consumption;
performance constraints;
custom NoC topology;
communication traces;
multiobjective optimization problem;
cost function minimization;
optimal MILP solutions;
85.
A novel algorithm for testing crosstalk induced delay faults in VLSI circuits
机译:
一种新颖的串扰诱导延迟故障在VLSI电路中的算法
作者:
Aniket
;
Arunachalam R.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
VLSI;
automatic test pattern generation;
crosstalk;
delays;
fault simulation;
integrated circuit testing;
VLSI circuits;
automatic test pattern generation;
critical paths;
crosstalk delays;
crosstalk induced delay faults;
deep submicron circuits;
delay fault;
delay t;
86.
Exact analytical equations for predicting nonlinear phase errors and jitter in ring oscillators
机译:
用于预测环振荡器中非线性相位误差和抖动的精确分析方程
作者:
Roychowdhury J.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
circuit noise;
jitter;
oscillators;
phase locked loops;
exact analytical equations;
golden mean;
injection locking prediction;
jitter prediction;
noise perturbations;
nonlinear phase errors prediction;
oscillator phase;
phase locked loop;
ring oscillators;
substrate;
87.
Application of Douglas-Peucker algorithm to generate compact but accurate IBIS models
机译:
Douglas-Peucker算法在Compace但精确的IBIS模型中的应用
作者:
Nandakumar G.N.
;
Patel N.
;
Reddy R.
;
Kothandaraman M.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
input-output stability;
buffer circuits;
SPICE;
Douglas-Peucker algorithm;
IBIS model generation;
input output buffer information specification;
input/output device;
V/I data;
V/T data;
IBIS Version3.2;
nonlinear sampling;
DP algorithm;
LVDS;
DPbasic;
88.
Coding for reliable on-chip buses: fundamental limits and practical codes
机译:
编码可靠的片上总线:基本限制和实用代码
作者:
Sridhara S.R.
;
Shanbhag N.R.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
crosstalk;
encoding;
error correction codes;
integrated circuit interconnections;
system buses;
system-on-chip;
0.13 micron;
10 mm;
32 bit;
CMOS technology;
bus encoding;
code construction;
decoding schemes;
encoding schemes;
error correction;
joint crosstalk avoidance;
89.
Detecting SEU-caused routing errors in SRAM-based FPGAs
机译:
检测SEU导致基于SRAM的FPGA中的路由错误
作者:
Reddy E.S.S.
;
Chandrasekhar V.
;
Sashikanth M.
;
Kamakoti V.
;
Vijaykrishnan N.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
SRAM chips;
block codes;
error detection;
fault tolerance;
field programmable gate arrays;
graph theory;
network routing;
CLB architecture;
FPGA LUT;
SEU-caused routing errors;
SRAM FPGA;
bridging faults;
circuit logic;
complex logic blocks;
configuration memory;
fault;
90.
An accurate probabilistic model for error detection
机译:
错误检测的准确概率模型
作者:
Rejimon T.
;
Bhanja S.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
belief networks;
error detection;
logic circuits;
probabilistic logic;
Bayesian networks;
IS-CAS'85 benchmark;
LIFE-DAG;
circuit logic;
detection probability;
error detection;
error susceptibility;
estimation time reduction;
logic induced fault encoded directed acyc;
91.
A low-power current-mode clock distribution scheme for multi-GHz NoC-based SoCs
机译:
基于GHz NOC的SOCS的低功率电流模式时钟分配方案
作者:
Ashok Narasimhan
;
Shantanu Divekar
;
Praveen Elakkumanan
;
Ramalingam Sridhar
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
delays;
integrated circuit interconnections;
microwave integrated circuits;
noise;
system buses;
system-on-chip;
timing;
0.18 micron;
bus delays;
bus noise;
clock distribution network;
current-mode clock distribution scheme;
current-mode clock signaling technique;
ne;
92.
Active noise cancellation using aggressor-aware clamping circuit for robust on-chip communication
机译:
使用侵略者感知钳位电路进行主动噪声消除,用于强大的片上通信
作者:
Katoch A.
;
Meijer M.
;
Jain S.K.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
crosstalk;
integrated circuit design;
integrated circuit interconnections;
integrated circuit noise;
system buses;
0.13 micron;
CMOS technology;
IC process technology;
active noise cancellation;
aggressor-aware clamping circuit;
aspect rat;
93.
An operational amplifier model for test planning at behavioral level
机译:
行为水平试验规划的运算放大器模型
作者:
Romero E.
;
Peretti G.
;
Marques C.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
operational amplifiers;
design for testability;
fault simulation;
circuit testing;
operational amplifier model;
test planning;
behavioral level;
test strategy evaluation;
fault injection;
fault simulation;
transistor level;
hypothetical OPA;
94.
Test methodologies in the deep submicron era - analog, mixed-signal and Rf
机译:
深度亚微米时代的测试方法 - 模拟,混合信号和RF
作者:
Chatterjee A.
;
Keshavarzi A.
;
Patra A.
;
Mukhopadhyay S.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
VLSI;
analogue integrated circuits;
built-in self test;
circuit analysis computing;
design for testability;
fault simulation;
integrated circuit testing;
mixed analogue-digital integrated circuits;
radiofrequency integrated circuits;
analog circuits;
behavioral mo;
95.
Physics and technology: towards low-power DSM design
机译:
物理与技术:走向低功耗DSM设计
作者:
Mukhopadhyay D.
;
Basu P.K.
;
Rao V.R.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
CMOS integrated circuits;
VLSI;
hot carriers;
impact ionisation;
integrated circuit design;
low-power electronics;
nanoelectronics;
quantum theory;
semiconductor device models;
tunnelling;
DSM CMOS IC;
basic physics;
deep sub-micrometer;
hot carrier effects;
hot carri;
96.
False path and clock scheduling based yield-aware gate sizing
机译:
基于FEATER-IPPARD门尺寸的虚假路径和时钟调度
作者:
Jeng-Liang Tsai
;
Dong Hyun Baik
;
Chung-Ping Chen C.
;
Saluja K.K.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
sequential circuits;
logic gates;
logic design;
integrated circuit yield;
scheduling;
delays;
timing;
timing margin;
timing yield;
false-path-aware gate sizing;
statistical-timing-driven clock scheduling;
true path lengths;
path delay uncertainty;
97.
Power optimization in current mode circuits
机译:
电流模式电路中的功率优化
作者:
Bhat M.S.
;
Jamadagni H.S.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
CMOS analogue integrated circuits;
comparators (circuits);
multivalued logic circuits;
CMOS analog;
approximation model;
current comparator circuit;
current mode circuits;
current-mode flash ADC designs;
literal generating circuits;
multiple-valued logic circuits;
98.
Synthesis of reversible circuits for testing with universal test set and C-testability of reversible iterative logic arrays
机译:
具有可逆迭代逻辑阵列的通用测试集测试可逆电路的可逆电路
作者:
Chakraborty A.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
design for testability;
fault simulation;
logic arrays;
logic gates;
logic testing;
low-power electronics;
AND gate;
EXOR gate;
Reed-Muller circuits;
design for test;
fault models;
iterative logic arrays;
k-wire controlled NOT gates;
low-power circuits;
multiple stuck;
99.
Influence of leakage reduction techniques on delay/leakage uncertainty
机译:
泄漏减少技术对延迟/泄漏不确定性的影响
作者:
Yuh-Fang Tsai
;
Vijaykrishnan N.
;
Yuan Xie
;
Irwin M.J.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
integrated circuit design;
circuit optimisation;
Monte Carlo methods;
leakage currents;
low-power electronics;
delays;
leakage reduction;
delay/leakage uncertainty;
integrated circuit design;
leakage power;
Monte Carlo analysis;
gate length;
stack forcing;
body biasing;
uncertainty-power-delay trade-off;
100.
Syntactic transformation of assume-guarantee assertions: from sub-modules to modules
机译:
假设保证断言的句法转换:从子模块到模块
作者:
Basu P.
;
Dasgupta P.
;
Chakrabarti P.P.
会议名称:
《International Conference on VLSI Design》
|
2005年
关键词:
specification languages;
temporal logic;
formal specification;
syntactic transformation;
assume-guarantee assertions;
modules;
RTL property;
assertion specification languages;
behavioral property;
input restriction;
interactive linear temporal logic;
module-level specifications;
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