Logic Synthesis for Low Power using Clock Gating and Rewiring

摘要

Traditionally, clock gating for power saving is mainly done at Register Transistor Level (RTL), while in a lower logical level some synthesis techniques, e.g. Observability Don't Care (ODC) can also be used to provide more power savings. In this paper, we propose an effective logic level ODC-based clock gating scheme that aims to reduce the intra-module dynamic power of sequential circuits. It is accompanied with a rewiring-based pruning scheme to trim down the incurred area overhead. Switching activity is put into account in the optimization processes. Extensive experimental results obtained by using ModelSim and PowerCompiler on the ISCAS-89 benchmarks showed that without rewired area trimming, an average of 40% on clock power and 12% on total dynamic power can be saved with a total cell area overhead of 6%. When rewiring was applied to trim down the area overhead, a similar clock power saving of 40% and an appealing 17% of total dynamic power saving can be achieved with area similar (-1%) to the original non ODC-clock-gated circuits.