Pattern Grading for Testing Critical Paths Considering Power Supply Noise and Crosstalk Using a Layout-Aware Quality Metric

摘要

Power supply noise and crosstalk are considered as the two major noise sources that negatively impact signal integrity in digital integrated circuits. In this paper, we propose a novel quality metric to evaluate path-delay fault test patterns in terms of their ability to cause excess delay on targeted critical paths. The proposed procedure quickly selects the best set of patterns for testing the critical paths under power supply noise and crosstalk effects. It also offers the design engineers a quick approach to evaluate the critical paths in static timing analysis (STA) and silicon to improve timing margin strategies. Simulation results demonstrate that the patterns selected by the proposed methodology generate the worst-case supply noise and crosstalk effects on target paths.