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A Linear Statistical Analysis for Full-Chip Leakage Power with Spatial Correlation

机译:空间相关性满芯片漏电的线性统计分析

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In this paper, we present an approved linear-time algorithm for statistical leakage analysis in the present of any spatial correlation condition (strong or weak). The new algorithm adopts a new set of uncorrelated variables over virtual grids to represent the original physical random variables and the grid size (thus of number of new random variables) is determined by the spatial correlation length. In this way, each physical variable is always represented by virtual variables locally. We prove that the number of neighboring virtual grids for each grid is not related to condition of spatial correlation, which leads to linear time complexity in terms of number of gates. We compute the gate leakage by the orthogonal polynomials based collocation method. The total leakage of a whole chip can be computed by simply summing up the coefficients of corresponding orthogonal polynomials for each grid. Furthermore, look-up table can be created to cache statistical information for each type of gates in library instead of calculating leakage for every single gate on chip. As a result, we end up with O(N) time complexity, where TV is the number of grids on chip. The proposed method has no restrictions on static leakage models, types of statistical distributions for leakage currents. Experimental results show that the proposed method is about 1000X faster than the recently proposed grid-based method [2] with similar accuracy and many orders of magnitude times over the Monte Carlo method.
机译:在本文中,我们在任何空间相关条件(强或弱)的目前提供了一种用于统计泄漏分析的批准的线性时间算法。新算法通过虚拟网格采用新的一组不相关变量,以表示原始物理随机变量,并且网格尺寸(因此,新的随机变量的数量)由空间相关长度确定。以这种方式,每个物理变量总是由本地的虚拟变量表示。我们证明每个网格的相邻虚拟网格的数量与空间相关条件无关,这导致栅极数量的线性时间复杂度。我们通过基于正交多项式的搭配方法计算栅极泄漏。通过简单地概括为每个网格的相应正交多项式的系数来计算整个芯片的总泄漏。此外,可以创建查找表以缓存库中每种类型的栅极的统计信息,而不是计算芯片上每个单个门的泄漏。结果,我们最终结束了O(n)时间复杂性,其中电视是芯片上的网格数。该方法对静态泄漏模型没有限制,泄漏电流的统计分布类型。实验结果表明,该方法比最近提出的基于网格的方法[2]快约1000倍,具有类似的准确性和蒙特卡罗方法的数量级数。

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