首页> 外文会议>Great lakes symposium on VLSI >Improving the Testability and Reliability of Sequential Circuits with Invariant Logic
【24h】

Improving the Testability and Reliability of Sequential Circuits with Invariant Logic

机译:具有不变逻辑的顺序电路的可测试性和可靠性

获取原文

摘要

In this paper, we propose the use of logic implications to enhance online error detection capabilities and to improve the testing efficiency of an integrated circuit. These logic implications are implemented in hardware and help to verify that expected invariant circuit relationships are satisfied during field operation. Thus, any implication violation will indicate the presence of an error due to some faulty circuit behavior. In addition, checking these logic implications in hardware will create additional circuit outputs, which may be useful for compacting n-detect test sets. Our results show that logic implications can provide significant error detection and test pattern count reduction with very limited hardware overhead.
机译:在本文中,我们提出了使用逻辑影响来增强在线错误检测能力并提高集成电路的测试效率。这些逻辑含义在硬件中实现,并帮助验证在现场操作期间满足预期的不变电路关系。因此,任何暗示违规都将指示由于某些故障电路行为而存在错误。此外,检查硬件中的这些逻辑含义将产生额外的电路输出,这对于压缩N检测测试集可能是有用的。我们的结果表明,逻辑含义可以提供显着的错误检测和测试模式计算,硬件开销非常有限。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号