As channel speeds approach 25 Gbps, near the expected maximum bandwidth for traditional copper-based PCBs, everyavailable tool to minimize total insertion loss in the board material system will need to be deployed. Material suppliers havedevised low-Dk, low-loss dielectrics and fiberglass, as well as ultra-low-profile copper foils. However, one of the lastremaining factors has not yet been quite so actively developed – the surface treatment applied by the PCB shop to theinnerlayer cores prior to lamination.In a previous paper presented at IPC, we described the effects of copper foil types, of varying levels of roughness, uponmeasured insertion loss of a stripline structure. We further showed the relative impact of different surface treatments (oxideand oxide alternative) which were then current in the industry. Recently, however, PCB chemical suppliers have begunoffering new treatments targeted specifically at insertion loss and surface roughness minimization, whereas priorformulations were aimed at maximization of bond strength and prevention of pink-ring.This paper builds upon our previous work by examining the insertion loss impact of such chemistry, holding constant thedielectric, test vehicle board design, and measurement technique used earlier. We are thus able to characterize the relativecontribution of lower-roughness innerlayer treatment chemistry to loss reduction, as compared to conventional formulations.
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