As channel speeds approach 25 Gbps, near the expected maximum bandwidth for traditional copper-based PCBs, every available tool to minimize total insertion loss in the board material system will need to be deployed. Material suppliers have devised low-Dk, low-loss dielectrics and fiberglass, as well as ultra-low-profile copper foils. However, one of the last remaining factors has not yet been quite so actively developed – the surface treatment applied by the PCB shop to the innerlayer cores prior to lamination. In a previous paper presented at IPC, we described the effects of copper foil types, of varying levels of roughness, upon measured insertion loss of a stripline structure. We further showed the relative impact of different surface treatments (oxide and oxide alternative) which were then current in the industry. Recently, however, PCB chemical suppliers have begun offering new treatments targeted specifically at insertion loss and surface roughness minimization, whereas prior formulations were aimed at maximization of bond strength and prevention of pink-ring. This paper builds upon our previous work by examining the insertion loss impact of such chemistry, holding constant the dielectric, test vehicle board design, and measurement technique used earlier. We are thus able to characterize the relative contribution of lower-roughness innerlayer treatment chemistry to loss reduction, as compared to conventional formulations.
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