A 2.5 GHz All-Digital Multiphase DLL and Phase Shifter in 65 nm CMOS using a Scalable Phase-to-Digital Converter

摘要

This work presents an all-digital multiphase DLL and phase shifter. A Phase-to-Digital Converter is used as a linear phase detector with 6 bit resolution and up to 76.9 MS/s sample rate at 2.5 GHz. A digitally controlled shunt-capacitor delay element makes use of the parasitic capacitance of transmission gates to provide a linear delay characteristic with 0.82 ps step size. This allows the use of a digital low-pass filter instead of an analog one and simplifies the control loop design resulting in an all-digital circuit that scales well with technology. A 7 bit phase interpolator with a PVT compensation loop is implemented to generate a phase shiftable clock signal with fine resolution. The digital DLL and phase shifter occupy 0.0048 mm² of active area in a 65 nm CMOS process and consume 3.9 mW from a 1.2 V supply. The measured RMS random jitter is 1.2 ps for the DLL and 1.4 ps for the phase shifter respectively.