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Study of Polyimide in Chip Package Interaction for Flip-Chip Cu-Pillar Packages

机译:倒装芯片铜柱封装的芯片封装相互作用中的聚酰亚胺研究

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Chip-package interaction (CPI) is a key area for achieving robust copper bump interconnection in flip-chip packages. Polyimide (PI) has been widely used in electronic package products to provide structural support to protect electronic devices from excessive stress. Passivation crack and LK/ELK delamination are two polyimide related failures in flip chip packages and pose significant challenges to achieving robust CPI design. A 3D finite element model was developed to evaluate the stress impact with the role of polyimide. For the passivation crack, a failure metric, radial passivation stress has been proposed to understand the passivation crack risk. The simulation shows that the in-plane radial stress of passivation layer is well correlated with the test results. The location of passivation crack matches the peak radial stress location within the passivation layer. The simulation compared the in-plane radial stress between package with and without PI and found the in-plane radial stress of passivation of packages with PI was significantly reduced compared with packages without PI layer. The simulation demonstrates PI can provide structural protection against tensile in-plane radial stress caused by thermal cooling after chip mass reflow. For ELK delamination, the ELK peel stress is correlated with experimental data. The simulation shows PI opening (PIO) has a big impact on the ELK peel stress. It has been found PIO plays a different role in ELK peel stress due to in-plane shear deformation and out-of-plane thermal expansion. When stress is induced due to in-plane shear deformation, smaller PIO and stiffer PI can provide better stress buffer on ELK layers. Larger PIO and stiffer PI can help to reduce the ELK peel stress induced by out-of-plane deformation. This study presents two failure stress metrics from fracture mechanics perspective and further understand the role of PI in flip chip Cu pillar packages.
机译:芯片封装相互作用(CPI)是实现倒装芯片封装中稳健的铜凸点互连的关键领域。聚酰亚胺(PI)已广泛用于电子封装产品中,以提供结构支撑,以保护电子设备免受过度的压力。钝化裂纹和LK / ELK分层是倒装芯片封装中与聚酰亚胺有关的两个故障,对实现可靠的CPI设计提出了重大挑战。开发了一个3D有限元模型,以评估在聚酰亚胺作用下的应力影响。对于钝化裂纹,已经提出了一种失效度量,即径向钝化应力,以了解钝化裂纹的风险。仿真表明,钝化层的面内径向应力与测试结果具有良好的相关性。钝化裂纹的位置与钝化层内的最大径向应力位置匹配。该仿真比较了有和没有PI的封装之间的平面内径向应力,发现与没有PI层的封装相比,具有PI的封装的钝化面内径向应力显着降低。仿真表明,PI可以提供结构保护,以防止芯片质量回流后由于热冷却而引起的拉伸面内径向应力。对于ELK分层,ELK剥离应力与实验数据相关。仿真显示PI开孔(PIO)对ELK剥离应力有很大影响。已经发现,由于面内剪切变形和面外热膨胀,PIO在ELK剥离应力中起着不同的作用。当由于面内剪切变形而产生应力时,较小的PIO和较硬的PI可以在ELK层上提供更好的应力缓冲。较大的PIO和较硬的PI可以帮助减少由平面外变形引起的ELK剥离应力。这项研究从断裂力学的角度提出了两种失效应力指标,并进一步了解了PI在倒装铜柱封装中的作用。

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