Controller Augmentation and Test Point Insertion at RTL for Concurrent Operational Unit Testing

摘要

Test point insertion methods to reduce the number of test patterns at register transfer level are required for the adaptability of traditional VLSI design flows and the reduction of time to search test point locations. In this paper, we propose a design-for-testability method at register transfer level to enable operational units as many as possible to be concurrently tested in scan testing. Using test point insertion and controller augmentation, the proposed design-for-testability method allocates input test registers and an output test register to inputs and an output of each operational unit in a data-path, respectively. Test compaction efficiency becomes high by enabling effective concurrent testing for operational units. Experimental results on high-level benchmark circuits show that our proposed method reduced the number of test patterns by 20% with 6.5% area overhead on average.