Test Pattern Generation to Detect Multiple Faults in ROBDD based Combinational Circuits

摘要

Reduced Ordered Binary Decision Diagram (ROBDD) based circuit syntheses is known to have complete testability under single stuck-at, multiple stuck-at and path delay fault models. In this paper we propose a test generation methodolgy for ROBDD based implementations. The test vectors required for all multiple stuck-at faults and delay faults are derived from the disjoint sum-of-products (DSOPs) representation thereby allowing test generation at design time with minimum effort.