Soft Error Analysis of MTJ-based Logic-in-Memory Full Adder: Threats and Solution

摘要

MTJ-based logic-in-memory architecture, where MTJ memory elements with spin-injection write capability are distributed over a logic-circuit plane, is attractive design template to realize ultra-low-power and reduced interconnection delay. Moreover, because of advantages of MTJ cells i.e., large resistance ratio, virtually unlimited endurance, fast read/write accessibility, scalability, CMOS-process compatibility, non-volatility and robustness to soft errors, this architecture is expected to realize soft error robustness. In this paper, a robust logic-in-memory full adder architecture is designed based on susceptibility analyses which is done in previous papers.