Due to the downscaling of transistor feature sizes, nowadays integrated circuits are more vulnerable to various effects that can cause faults during operation. Appropriate mechanisms for handling these faults in the field are required to meet certain dependability demands nonetheless. At the same time, the overhead in chip area and power consumption that is caused by such fault tolerance techniques needs to be reasonable. This calls for a dependability aware design space exploration which carefully evaluates the costs and benefits of various fault tolerant implementations of the system. This paper first introduces a tool that supports this design space exploration for hardware redundancy based fault tolerance. Among other features, it offers very fast overhead estimations for the supported set of fault tolerance techniques. The paper describes in detail how the estimations of the power overhead are performed. The accuracy of these estimations is evaluated by comparison with power analysis results obtained by a commercial EDA tool.
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