Hot-carrier and BTI damage distinction for high performance digital application in 28nm FDSOI and 28nm LP CMOS nodes

摘要

We use dedicated test structures for high performance low power (LP) CMOS nodes designed with 28nm FDSOI and 28nm LP devices. These allow to distinguish AC high frequency dependence as a function of high temperature (125°C) experiments for Bias Temperature Instability (BTI) and Hot-Carrier Damage (HCD) (1) for inverter chains (buffers) and logic gates in order to obtain AC-DC ratios (2) in standard logic gate paths for timing degradation with activity as a variable. This shows that NBTI remains the worst-case of damage at high temperature with a frequency independence due to the limited effect of relaxation with activity lowering (ton/toff) while HCD still represents a significant damage contribution at lower temperature due to the frequency and pulse shape dependences during transients. An accurate quantitative analysis is checked in a data path example with ELDO simulations that distinguishes each contribution.