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Process Integration and Performance Evaluation of Germanium-based Quantum Well Channel MOSFETs for Sub-22nm Node Digital CMOS Logic Technology

机译：用于亚22纳米节点数字CMOS逻辑技术的基于锗的量子阱沟道MOSFET的工艺集成和性能评估

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作者
Lee, Se-Hoon.;
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作者单位

The University of Texas at Austin.;

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授予单位 The University of Texas at Austin.;
学科 Nanotechnology.;Electrical engineering.
学位 Ph.D.
年度 2011
页码 203 p.
总页数 203
原文格式 PDF
正文语种 eng
中图分类
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专利

1. Design of single-gate n-channel and p-channel MOSFETs with enhanced current-drive due to simultaneous switching of front and back channels in SOI CMOS technology [J] . B. Bindu, N. Lakshmi, K.N. Bhat, Solid-State Electronics . 2006,第7a8期

机译：通过同时切换SOI CMOS技术中的前，后通道，增强电流驱动的单栅极n沟道和p沟道MOSFET的设计
2. Impact of channel thickness and spacer length on logic performance of p-Ge-Si hybrid CMOSFETs for ULSI applications [J] . De Suchismita, Tewari Suchismita, Biswas Abhijit D., Superlattices and microstructures . 2017,第sepa期

机译：沟道厚度和间隔长度对ULSI应用中p-Ge / n-Si混合CMOSFET逻辑性能的影响
3. MOSFET modeling for design of ultra-high performance infrared CMOS imagers working at cryogenic temperatures: Case of an analog/digital 0.18 urn CMOS process [J] . P. Martin, A.S. Royet, F. Guellec, Solid-State Electronics . 2011,第1期

机译：用于低温工作的超高性能红外CMOS成像器设计的MOSFET建模：0.18 umn模拟/数字CMOS工艺案例
4. High voltage MOSFETs integration on advanced CMOS technology: Characterization of thick gate oxides incorporating high k metal gate stack from logic core process [C] . Dann Morillon, Franck Julien, Jean Coignus, 2017 International Conference of Microelectronic Test Structures . 2017

机译：在先进的CMOS技术上集成高压MOSFET：结合逻辑内核工艺中的高k金属栅叠层，对厚栅氧化物进行表征
5. Low-k materials as interlayer dielectrics in CMOS: The effects of deposition and processing on N-channel MOSFET's characteristics. [D] . Trabzon, Levent. 2000

机译：低k材料作为CMOS中的层间电介质：沉积和处理对N沟道MOSFET特性的影响。
6. pMOSFETs Featuring ALD W Filling Metal Using SiH4 and B2H6 Precursors in 22 nm Node CMOS Technology [O] . Guilei Wang, Jun Luo, Jinbiao Liu, 2017

机译：采用22 nm节点CMOS技术的SiH4和B2H6前体的ALD W填充金属功能的pMOSFET
7. Performance of buried channel n-type MOSFETs in 0.18-μm CMOS image sensor process [O] . Stefanov Konstantin D., Zhang Zhige, Damerell Chris, 2013

机译：掩埋沟道n型mOsFET在0.18μmCmOs图像传感器工艺中的性能

Process Integration and Performance Evaluation of Germanium-based Quantum Well Channel MOSFETs for Sub-22nm Node Digital CMOS Logic Technology

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