Design of a 0.13μm CMOS Front-end for 4.5-5.5GHz Radar Sensor Chip

摘要

This paper addresses the problem of 4.5-5.5GHz direct-conversion front-end design in a SOC-based radar sensor chip for vital signal detection. The front-end is characterized by a broadband low noise amplifier (LNA) and a PMOS switching-type double-balanced mixer. The LNA and the mixer co-design introduces both noise cancellation topology and linearization technology, obtaining input matching, noise suppression and IIP3 enhancement simultaneously at carried 5GHz. The current density of the transconductance stage is dictated transcendentally, and ensured by thermal robustness bias circuitry. Stack bias circuitry is considered to suppress flicker noise. The maximum conversion gain (CG), IIP3 and minimum double-sideband noise figure is 20.7dB, 8.58dBm, 7.9dB, respectively. The voltage control oscillator (VCO) is tunable between 4.5-5.5GHz with phase noise below -120dBc/Hz at 1MHz offset. The best phase noise at 1MHz offset is -132dBc/Hz, given that the front end consumes 40mW from 1.2V supply.