Wafer thinning for high-density three dimensional integration _ 12-inch wafer-level 3D-LSI program at GINTI

摘要

Thinning down large scale integrated-chip (LSI) wafers to below 50 µm thickness is inevitable for the wafer-to-wafer (WtW) process as well as chip-to-wafer (CtW) or chip-to-chip (CtC) processes in three-dimensional LSI integration. In this work we have optimized edge-trimming and back-grinding followed by chemical-mechanical polishing processes for WtW integration of 12-inch LSI wafer with thickness ≤ 50 µm. After optimization, we were able to achieve the total thickness variation (TTV) of less than 200 nm in the 50 µm-thick LSI wafers. Also, it was found that the smaller TTV value of temporarily bonded wafer before wafer thinning greatly helps to reduce the TTV in the back-ground and polished wafers. We successfully integrated 50 µm-thick 8- and 12-inch LSI wafers to their respective passive interposers using Cu-TSVs, and the electrical properties of TSVs were evaluated.