Effects of DC bias and spacing on migration of sintered nanosilver at high temperatures for power electronic packaging

摘要

Joining semiconductor chips at low temperatures (below 300 °C) by sintering nanosilver paste is emerging as an alternative, lead-free solution for power electronic packaging, especially high-temperature applications, because of high melting temperature of silver (961 °C). However, silver is susceptible to migration. In this paper, we studied effects of temperature, DC bias, and electrode spacing on migration of sintered nanosilver on an alumina substrate. The “lifetime” of silver migration, which is defined as the time at which the leakage current reaches 1 mA, increases with decreasing bias voltage, increasing spacing between the nanosilver electrodes, or decreasing temperature. A phenomenological model was obtained to predict the lifetime of migration of sintered nanosilver.