Design of Low-Power Double Edge-Triggered Flip-Flop Circuit

摘要

In this paper, we proposed a double edge-triggered (DET) flip-flop suitable for low-power applications. In addition, the proposed flip-flop can be implemented with fewer transistors than any previous circuit. Simulations have verified the correct operation of the proposed DET flip-flop, for a variety of clock and data rates. Simulation results indicated that the proposed circuit is capable of significant delay and power saving.