Design of high performance double edge-triggered flip-flops

摘要

A methodology for constructing double edge-triggered flip-flopsn(DETFFs) from existing latches, which removes the need for completenflip-flops or the presence of clocked nodes in the combining section isnpresented. The application of this methodology to designing DETFFs basednon latches constructed from pass transistor/transmission gates, truensingle-phase clocked structures, and differential logic is investigated.nThe resulting DETFFs deliver high performance and do not suffer from thenproblems of charge sharing, charge coupling, reduced voltage swing, poornsupply voltage scaling properties, and excessive power dissipationnplaguing existing DETFFs