We present a formula of short-circuit power dissipation for static CMOS logic gates. By representing short-circuit current by a piece-wise linear function and considering current flowing from the input node to the output node through gate capacitances, the accuracy is improved significantly. The error of our formula for a CMOS inverter is less than 15% from circuit simulation in most cases. We also derive delay formulae considering the short-circuit current and the current flowing through gate capacitance. The error of this formula is smaller than 13% in our experiments. Since these formulae calculate the short-circuit power dissipation and the delay accurately and quickly, they can be applied to power sensible CAD tools.
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