A Simulator of Memory Management for Low Power

摘要

This paper describes a simulator of memory management that focuses on low power management. Embedded systems equip increasingly large size of main memories, and the main memory consume large part of energy of total systems. For embedded systems, main memory consists of on-chip memory, which is on a board including a processor, and off-chip one. Accesses of a processor to the on-chip memory are performed fast and with low power. On the other hand, accesses to the off-chip memory are performed slowly and with high power. Therefore, memory management between the on-chip memory and the off-chip one is important from the viewpoint of low power as well as achieving high performance. We develop a simulator to study the memory management. Since the simulator consists of some modules, the simulator can provide feasibility including memory management policy, target hardware architecture, and so on. This paper describes the simulator and preliminary results of the memory management with the simulator.