Evaluating Device Reliability Using Wafer-level Methodology

摘要

This paper demonstrates the viability of wafer-level methods as a means of evaluating device reliability using special reliability test structures and process control monitors (PCM). The results presented illustrate how this methodology can be employed to rapidly and effectively assess the impact of process or material changes on over-all reliability. The wafer-level methodology provides a quick feedback loop for the manufacturing group enhancing their ability to continuously improve on their processes.