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Massively parallel wafer-level reliability system and process for massively parallel wafer-level reliability testing
Massively parallel wafer-level reliability system and process for massively parallel wafer-level reliability testing
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机译:大规模并行晶圆级可靠性系统和过程,用于大规模并行晶圆级可靠性测试
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摘要
A massively parallel wafer-level reliability system to test a reliability of wafers includes: a test platform; stations disposed on the test platform, wherein an individual test station receives a wafer and includes: a chuck disposed on the test platform; a probe including contactors that electrically contact the wafer; and a temperature controller to control a temperature of the wafer; a control platform disposed among the test stations; and a system controller to independently control the test stations and that is in electrical communication with the temperature controller, wherein the reliability of the wafers is tested in parallel by the test stations.
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