Critical Dimension Control of 0.18umm Logic with Dual Polysilicon Gate

摘要

A dual polysilicon gate structure is required to increase the circuit speed and the packing density, as well as the low-power operation as the design rule of CMOS scales down to sub-0.25umm. In order to get the superior device performance of 0.18umm logic device, we need to do the gate implantation prior to polysilicon etch. The critical dimension (CD) different between NMOS and PMOS during polysilicon gate etching needs to be reduced for matching the design drive current of NMOS and PMOS. In this work, the pressure, the bias power, the total flow of CF_4 and Cl_2 and the N_2 flow are used for the investigation of 0.18 umm device during the dual gate etch. After optimizing all etch parameters, the CD offset is small (0.007 umm) between NMOS and PMOS. The vertical profile (about 88-89 degree), the small bias (about 0.003um at PMOS gate and -0.004umm at NMOS gate), and CD micro-loading (about 0.005 umm) are obtained using in-situ BARC and polysilicon etching. The result of pitting free, stringers free and notching free after dual polysilicon etching is achieved, and the remaining thickness of deep UV photoresist at shoulder is about 800-880A. From this study, both good performance device and the process controllability are obtained with in-situ bottom anti-reflective coating and dual polysilicon gate etching.