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Process for etching polysilicon gates with good mask selectivity, critical dimension control, and cleanliness

机译:具有良好的掩模选择性,关键尺寸控制和清洁度的多晶硅栅极蚀刻工艺

摘要

The present invention provides a process of etching polysilicon gates using a silicon dioxide hard mask. The process includes exposing a substrate with a polysilicon layer formed thereon to a plasma of a process gas, which includes a base gas and an additive gas. The base gas includes HBr, Cl2, O2, and the additive gas is NF3 and/or N2. By changing a volumetric flow ratio of the additive gas to the base gas, the etch rate selectivity of polysilicon to silicon dioxide may be increased, which allows for a thinner hard mask, better protection of the gate oxide layer, and better endpoint definition and control. Additionally, when the polysilicon layer includes both N-doped and P-doped regions, the additive gas includes both NF3 and N2, and by changing a volumetric flow ratio of NF3 to N2, the etching process may be tailored to provide optimal results in N/P loading and microloading.
机译:本发明提供了一种使用二氧化硅硬掩模蚀刻多晶硅栅极的工艺。该工艺包括将其上形成有多晶硅层的基板暴露于工艺气体的等离子体中,该工艺气体包括基础气体和添加气体。基础气体包括HBr,Cl 2 ,O 2 ,添加气体为NF 3 和/或N 2 。通过改变添加气体与基本气体的体积流量比,可以提高多晶硅对二氧化硅的蚀刻速率选择性,从而实现更薄的硬掩模,更好的栅氧化层保护以及更好的终点定义和控制。另外,当多晶硅层同时包含N掺杂区和P掺杂区时,添加气体同时包含NF 3 和N 2 ,并且通过改变体积流量比从NF 3 到N 2 ,可以定制蚀刻工艺以在N / P加载和微加载中提供最佳结果。

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