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Wafer-Level Packaging Technology for Extended Global Wiring and Inductors

机译:晶圆级封装技术,用于扩展的全局布线和电感器

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摘要

Wafer lever packaging (WLP) technology, originally introduced for thin film redistribution layers, offers novel opportunities for extended global wiring and passives and has been used to integrate transmission lines and state-of-the-art high Q on-chip inductors on top of a five-levels-of-metal (5ML) Cu/oxide back-end of line (BEOL) 20Ω.cm silicon process. The transmission lines and inductors are realized above the passivation using thick post-processed dielectric (BCB, ε_r=2.65) and Cu layers. Measurements on the BEOL before and after post-processing show no significant shifts for all 5 metal layers. Post-processed SOD transmission lines have losses below -0.1dB/mm@25GHz; a 1nH inductor has a peak Q-factor of 38 at 4.7 GHz with resonance frequency (F_(res)) of 29GHz, the Q-factor tops 30 over 2.6-8.6GHz. Patterned poly silicon ground shields further improve the performance: a Q-factor increase of 90% was demonstrated at 7GHz for a 2.25nH inductor.
机译:晶圆杠杆包装(WLP)技术最初是为薄膜再分配层引入的,它为扩展全局布线和无源器件提供了新的机遇,并已被用于在其顶部集成传输线和最新的高Q片上电感器五层金属(5ML)铜/氧化物线路后端(BEOL)20Ω.cm硅工艺。传输线和电感器是在钝化层上方使用厚的后处理电介质(BCB,ε_r= 2.65)和Cu层实现的。后处理前后在BEOL上的测量结果表明,所有5个金属层均无明显变化。后处理的SOD传输线的损耗低于-0.1dB/mm@25GHz;一个1nH电感器在4.7 GHz时的峰值Q因子为38,谐振频率(F_(res))为29GHz,在2.6-8.6GHz范围内该Q因子最高为30。图案化的多晶硅接地屏蔽进一步改善了性能:对于2.25nH的电感器,在7GHz频率下Q值提高了90%。

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