A multi-phase clock design for super high-speed time interleaved analog-to-digital converter

摘要

In this paper, we present a multi-phase clock (MPC) which is used in a super high-speed time interleaved analog-to-digital converter (TI ADC). To meet the timing requirements of the whole ADC, timing design between channels must be performed carefully, meanwhile, because the signal-to-noise ratio(SNR) of the whole ADC is restrained to the time-skew and jitter performance of the multi-phase clock, lower these timing errors is very important for TI ADC. We use a shift register based multi-phase generator to implement the multiphase relationship between sub-clocks. Digital calibration of the time-skew of single channel clock and serial peripheral interface (SPI) are adopted to lower timing errors between them further more. As a demonstration, a 4-phase clock is implemented, the presented clock circuit is used in a 8bit 5Gsps TI ADC. The whole TI ADC is implemented using a 0.18μm SiGe BiCMOS process. As a result of test, the whole ADC has a SNR of about 45dB at the input frequency of 495MHZ.