FORMING 3D TRANSISTORS USING 2D VAN DER WAALS MATERIALS

摘要

The method includes etching a dielectric layer to form a dielectric fin, depositing a transition metal dichalcogenide layer on the dielectric fin, and a first anisotropy with respect to the transition metal dichalcogenide layer. performing an etching process. A horizontal portion of the transition metal dichalcogenide layer is removed, and a vertical portion of the transition metal dichalcogenide layer on the sidewalls of the dielectric fin remains to form a vertical semiconductor ring. The method further includes forming a gate stack on a first portion of the vertical semiconductor ring, and forming a source/drain contact plug, wherein the source/drain contact plug is formed of a second portion of the vertical semiconductor ring. in contact with the sidewall.