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STATISTICAL LOGIC TEST SYSTEM HAVING A WEIGHTED RANDOM TEST PATTERN GENERATOR

机译:具有加权随机测试模式生成器的统计逻辑测试系统

摘要

A system for testing complex circuitry primarily in large scale integration where a great number of inputs and outputs must be tested and the internal circuitry is inaccessible. The test system has a weighted random number generator which applies a test signal to some input terminals of the logic under test more frequently than others. A particular input terminal to the logic under test can be accessed in proportion to the circuit switching activity associated with accessing that particular terminal.
机译:一种主要在大规模集成中测试复杂电路的系统,其中必须测试大量的输入和输出,并且内部电路不可访问。该测试系统具有一个加权随机数发生器,该发生器将测试信号比其他信号更频繁地施加到被测逻辑的某些输入端子上。可以与与访问该特定端子相关联的电路切换活动成比例地访问被测逻辑的特定输入端子。

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