Integration of two semiconductor chips inside standard outline package - uses solder bumps on both dice which are bonded face-to-face in lead-on-chip configuration to lead frame

摘要

The multi-chip package consists of an upper and a lower semiconductor chip and a leadframe, whereby both chips are electrically connected with lead frame fingers. The chips feature solder-bumps, pref. solder-balls, consisting of an Pb-Sn alloy with, pref. a m.pt. higher than the cure temp. of the epoxy moulding cpd. used to encapsulate the device, on the bond pads and attachment to the lead fingers is by soldering. The solder-bumps are pref. located on the 2 chips along the same longitudinal line and pref. alternating between upper and lower die. Also claimed is orientation of the bumps on lower and upper chip along 2 parallel longitudinal lines and bond pads from upper and lower chips being bonded alternatingly to the lead frame fingers forming 2 comb patterns which are offset from each other by half the pitch between adjacent fingers or with butting lead fingers. An assembly process flow is also claimed. USE/ADVANTAGE - The process eliminates the wire bonding process, which allows the height above the chips to be reduced and which reduces electrical noise and cross-coupling. The process allows 2 chips to be bonded simultaneously inside a single package, reducing the amount of work required and increasing the density of the device without increasing the package dimensions. Suitable package outlines are Quad flat-pack (QFP), Thin Small Outline Package (TSOP), other SOP and SOJ packages and Mini Square package (MSP).