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ELECTRICAL CHARACTERISTICS TESTING METHOD FOR CMOS DIGITAL INTEGRATED CIRCUIT

机译:CMOS数字集成电路的电气特性测试方法

摘要

PURPOSE: To obtain an electrical characteristics testing method for CMOS digital integrated circuit by which defective MOS transistor in a CMOS digital integrated circuit can be detected easily in a short time. ;CONSTITUTION: Electrode terminal 4 of P-channel MOS transistor substrate is isolated from a power supply terminal 5, i.e., the source electrode terminals of P-channel MOS transistors 8, 9. Furthermore, electrode terminal 6 of an N-channel MOS transistor substrate is isolated from a ground terminal, i.e., the source electrode terminal of an N-channel MOS transistor 11. All terminals other than the electrode terminal 4 of the P-channel MOS transistor substrate, are set at an identical potential having a difference from the potential at the electrode terminal 4 of the P-channel MOS transistor thus detecting a defective MOS transistor based on measurements of leak current.;COPYRIGHT: (C)1993,JPO&Japio
机译:目的:获得一种用于CMOS数字集成电路的电特性测试方法,通过该方法可以在短时间内轻松检测出CMOS数字集成电路中的有缺陷的MOS晶体管。 ;构成:P沟道MOS晶体管基板的电极端子4与电源端子5隔离,即P沟道MOS晶体管8、9的源电极端子。此外,N沟道MOS晶体管的电极端子6基板与接地端子即N沟道MOS晶体管11的源电极端子隔离。除P沟道MOS晶体管基板的电极端子4以外的所有端子均设置为相同电位,其电位与P沟道MOS晶体管的电极端子4上的电位,从而基于泄漏电流的测量来检测有缺陷的MOS晶体管。版权所有:(C)1993,JPO&Japio

著录项

  • 公开/公告号JPH05340991A

    专利类型

  • 公开/公告日1993-12-24

    原文格式PDF

  • 申请/专利权人 NEC CORP;

    申请/专利号JP19920150451

  • 发明设计人 TAKAYAMA SHOJI;

    申请日1992-06-10

  • 分类号G01R31/26;H01L21/66;

  • 国家 JP

  • 入库时间 2022-08-22 04:47:18

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