Substrate potential generating circuit generating substrate potential of lower level and semiconductor device including the same

摘要

A substrate potential generating circuit can generate a lower substrate potential. The substrate potential generating circuit includes a clock signal generating circuit and first and second charge pump circuits. The first charge pump circuit including a p-channel MOS transistor having its source electrode connected to the semiconductor substrate applies a first negative potential to the drain electrode by capacitive coupling of a capacitor. The second charge pump circuit including first and second sub-charge pump circuit applies a third negative potential to the gate electrode when the first negative potential is applied to the drain electrode, and thereafter provides a second potential by lowering the third potential. As a result, the p- channel MOS transistor is turned on until a substrate potential is brought into a potential equal to the first potential applied to the drain electrode, lowering the substrate potential to the first potential.