首页> 外国专利> METHOD AND APPARATUS FOR TESTING ELECTRONIC MEMORIES FOR THE PRESENCE OF MULTIPLE CELL COUPLING FAULTS

METHOD AND APPARATUS FOR TESTING ELECTRONIC MEMORIES FOR THE PRESENCE OF MULTIPLE CELL COUPLING FAULTS

机译:用于检测存在多个单元耦合故障的电子存储器的方法和装置

摘要

A method of testing a random access memory (RAM) for single V-coupling faults by establishing a first current value for each cell, for each cell and for each of m data backgrounds, generating a data bit corresponding to an element of an (n, V - 1)exhaustive matrix, and for each of m data backgrounds: (1) applying a read write sequence to each cell; and (2) for each background except the mth background, updating the current value of all cells according to the data bits corresponding to that cell; reading each cell of the RAM; and discarding or repairing the RAM if a cell coupling fault is apparent from the series of values read from the cells of the RAM. Data bits are generated by a matrix reconstruction method or a pseudo-random generator using a hashing of the address of the cell to which the data bit is to be applied. The logical function may be the element of the (n, V 1)-exhaustive matrix irrespective of the current of the cell or an exclusive-or of the complement of the background code logic bit and the first current value of the cell. Apparatus for testing a random access memory (RAM) has a PROM containing background code logic bits corresponding to an (n0, V - 1)-exhaustive matrix where n0 columns; and a data bit generator for generating data bits from the matrix stored in the PROM. A built in apparatus for testing a random access memory (RAM) having n cells includes a data bit generator that generates pseudo-random data bits from a hashing of the address of the RAM cell to which the data bit is to be applied.
机译:一种通过为每个单元,每个单元以及m个数据背景中的每一个建立第一电流值,生成与第n个元素对应的数据位来测试单个V耦合故障的随机存取存储器(RAM)的方法,V-1)穷举矩阵,并且对于m个数据背景中的每一个:(1)对每个单元格应用读写序列; (2)对于除第m个背景以外的每个背景,根据该单元对应的数据位,更新所有单元的当前值;读取RAM的每个单元;如果从RAM的单元读取的一系列值中明显出现单元耦合故障,则丢弃或修复RAM。数据位是通过矩阵重构方法或伪随机数生成器使用将要应用数据位的单元地址的哈希值生成的。逻辑函数可以是(n,V 1)穷举矩阵的元素,而与单元格的电流或背景代码逻辑位和单元格的第一电流值的补码的异或无关。用于测试随机存取存储器(RAM)的设备具有包含与(n0,V-1)穷举矩阵相对应的背景代码逻辑位的PROM,其中n0列;数据位发生器,用于从存储在PROM中的矩阵中产生数据位。用于测试具有n个单元的随机存取存储器(RAM)的内置设备包括数据位生成器,该数据位生成器根据将要应用该数据位的RAM单元的地址的哈希值生成伪随机数据位。

著录项

  • 公开/公告号CA2129390A1

    专利类型

  • 公开/公告日1996-02-04

    原文格式PDF

  • 申请/专利权人 TELECOMMUNICATIONS RESEARCH LABORATORIES;

    申请/专利号CA19942129390

  • 发明设计人 COCKBURN BRUCE FORDYCE;

    申请日1994-08-03

  • 分类号G01R31/26;

  • 国家 CA

  • 入库时间 2022-08-22 03:50:42

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