首页> 外国专利> Floating point addition and subtraction arithmetic circuit performing preprocessing of addition or subtraction operation rapidly

Floating point addition and subtraction arithmetic circuit performing preprocessing of addition or subtraction operation rapidly

机译:浮点加减运算电路可快速进行加减运算的预处理

摘要

A floating point addition and subtraction circuit comprises a comparison subtraction circuit (10) receiving two operands to be processed for making a comparison in the size between their exponent parts so to subtract the smaller exponent part from the larger one, said comparison subtraction circuit providing the comparison result and the subtraction resu a mantissa selecting circuit (20) and a shift circuit (30) for aligning the mantissa of the operand; a trailing zero counting circuit (50) for counting the number of zeros successively positioned in the high order direction from the least significant bit of the mantissa of the operand having the smaller operand; a comparator circuit (51) for making a comparison between the counting result and the subtraction result by the comparison subtraction circuit, thereby to detect a sticky bit according to the comparison resu and an absolute value addition and subtraction arithmetic circuit (60), receiving the mantissas of the two operands having been aligned and the detected sticky bit, for performing addition or subtraction operation on operand.
机译:浮点加减电路包括比较减法电路(10),该比较减法电路接收两个要处理的操作数,以比较它们的指数部分的大小,以便从较大的指数部分减去较小的指数部分,所述比较减法电路提供比较结果和减法结果;尾数选择电路(20)和移位电路(30),用于对齐操作数的尾数;后置零计数电路(50),用于从具有较小操作数的操作数的尾数的最低有效位开始,对在高阶方向上连续定位的零的数目进行计数;比较器电路(51),用于通过比较减法电路对计数结果和减法结果进行比较,从而根据比较结果检测出粘性位;绝对值加减运算电路(60),接收已对齐的两个操作数的尾数和检测到的粘性位,以对操作数进行加减运算。

著录项

  • 公开/公告号EP0786721A1

    专利类型

  • 公开/公告日1997-07-30

    原文格式PDF

  • 申请/专利权人 NEC CORPORATION;

    申请/专利号EP19970101394

  • 发明设计人 KAWAGUCHI TADAHARUC/O NEC KOFU LTD.;

    申请日1997-01-29

  • 分类号G06F7/50;

  • 国家 EP

  • 入库时间 2022-08-22 03:19:28

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