A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits

摘要

This paper presents a unified logic for flagged prefix addition-subtraction that eliminates the need to perform constant addition and subtraction in two separate blocks. The logic is based on a modified algorithm for constant subtraction that allows us to achieve the unification which is not possible with traditional algorithms. Thus we are able to eliminate the most crucial challenge that practical implementation of constant flagged structures faces. We present the applications of the proposed logic in the exponent biasing circuits of a binary floating-point unit and in a signed-digit decimal adder. Synthesis results show that close to 42% reduction in area and 24% in power is achieved when the unified logic is used with numerically large values like exponent biases. Even for numerically smaller constants like those used in signed-digit decimal adders, we get substantial benefit, with the area reducing by 12.3% and power by 12.4% in this case, thereby demonstrating the effectiveness of the proposed scheme for both small and large constants. Additionally, the propagation delay does not vary by more than 5-6% and power-delay product comes down by almost 20% in both the cases. On account of their power and area efficiency, proposed designs incorporating the unified logic can serve as good frameworks for Embedded DSP and financial applications.