High speed comparator having two differential amplifier stages and latch stage

摘要

In a comparator including a first differential amplifier stage (1) for amplifying the difference in potential between input signals (V_in1, V_in2), a second differential amplifier stage (2) for amplifying the difference in potential between output signals (V₁, V₂) of the first differential amplifier stage (1), and a latch stage (3) for positively feeding output signals (V₃, V₄) of the second amplifier stage back thereto, a first differential switch circuit (4) alternately switches the second differential amplifier stage and the latch stage, and a second differential switch circuit (5) alternately switches the first differential amplifier stage and the latch stage.