CMOS output buffer to reduce the oscillation of voltage negative feedback unit (NEGATIVE FEEDBACK TO REDUCE VOLTAGE OSCILLATION IN CMOS OUTPUT BUFFERS)

摘要

the CMOS output buffer with voltage oscillation is a negative feedback means to the application. the buffer is full up transistor (P1), full down transistor (N1), a reference voltage generating circuit (44) and the second reference voltage generating circuit (54) and the first negative feedback circuit (48) and a second negative feedback circuit (58) structure. the first and the second negative feedback from the internal power supply potential and ground potential between the anode and the up / down - down drive transistor of the gate with the combination between each layer, the charge / discharge current change rate decreased.