METHOD FOR FACILITATING TEST BY FREQUENCY DIVIDER CIRCUIT, AND FREQUENCY DIVIDER CIRCUIT WITH TEST CIRCUIT

摘要

PROBLEM TO BE SOLVED: To obtain a method for facilitating tests by a frequency divider circuit that verifies a timing, even at test operation by adding a test circuit to the frequency divider circuit so as to reduce a test pattern and to obtain the frequency divider circuit with the test circuit. SOLUTION: This frequency divider circuit with a test circuit is roughly configured with a decoder circuit section, an adder circuit section, a selector section and a flip-flop (hereinafter called an F/F'). The frequency divider circuit receives a test signal TEST and a control signal CONT and a circuit for reducing a period of a frequency division clock signal in use to a shorter period is inserted to the pre-stage of the F/F.