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SYSTEM AND METHOD FOR CHECKING DESIGN RULE AND DESIGN RULE CHECK PROGRAM RECORDING MEDIUM

机译:检查设计规则和设计规则检查程序记录介质的系统和方法

摘要

PROBLEM TO BE SOLVED: To design an integrated circuit which surely satisfies a design rule and also to shorten the time required for verifying whether a relevant rule is satisfied. ;SOLUTION: In the system where a design s checked about an integrated circuit consisting of plural cells, a prescribed distance is set between each of input/output cells 2 arranged around a cell area 1 and other input/output cells. Since this set distance differs according to the wiring materials, a space is secured by a distance corresponding to the wiring material that requires the longest distance. In other words, the cell space is decided in response to the minimum wiring space corresponding to the wiring material that is decided by a design rule. It is verified whether the integrated circuit that is produced according to the decided cell space is accordant with the design rule. Thus, the time required for verification is shortened since verification can be omitted about combinations with other cells.;COPYRIGHT: (C)2001,JPO
机译:要解决的问题:设计一种既可以满足设计规则的集成电路,又可以缩短验证是否满足相关规则所需的时间。 ;解决方案:在检查由多个单元组成的集成电路的设计的系统中,在围绕单元区域1布置的每个输入/输出单元2与其他输入/输出单元之间设置了规定的距离。由于该设定距离根据配线材料而不同,因此通过与需要最长距离的配线材料对应的距离来确保空间。换句话说,单元空间是响应于与由设计规则确定的布线材料相对应的最小布线空间而确定的。验证根据确定的单元空间产生的集成电路是否符合设计规则。因此,由于可以省略关于与其他单元格的组合的验证,因此缩短了验证所需的时间。版权所有:(C)2001,JPO

著录项

  • 公开/公告号JP2001273349A

    专利类型

  • 公开/公告日2001-10-05

    原文格式PDF

  • 申请/专利权人 SEIKO EPSON CORP;

    申请/专利号JP20000084883

  • 发明设计人 OKI YUJI;

    申请日2000-03-24

  • 分类号G06F17/50;H01L21/82;

  • 国家 JP

  • 入库时间 2022-08-22 01:29:31

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