首页> 外国专利> Formal verifying method for development in data processor involves executing verification algorithm using one limit of signal envelope, and limiting state-space search by using verification algorithm

Formal verifying method for development in data processor involves executing verification algorithm using one limit of signal envelope, and limiting state-space search by using verification algorithm

机译:用于数据处理器中的形式化验证的方法包括:使用信号包络的一个限制执行验证算法,并使用验证算法限制状态空间搜索

摘要

A tracing program is determined by using a verification algorithm. The result of the determination of the tracing program is indicated on a graphical user interface. One limit of a signal envelope is then changed. The execution of the verification algorithm is then performed by using one limit of the signal envelope, and a state-space search is limited by the use of the verification algorithm. Independent claims are also included for the following: (a) a device for formal verification of development in data processor; (b) and a computer program for formal verification of development in data processor.
机译:通过使用验证算法确定跟踪程序。确定跟踪程序的结果显示在图形用户界面上。然后改变信号包络的一个极限。然后,通过使用信号包络的一个限制来执行验证算法,并且通过使用验证算法来限制状态空间搜索。还包括以下方面的独立权利要求:(a)用于对数据处理器中的开发进行正式验证的设备; (b)以及用于对数据处理器中的开发进行形式验证的计算机程序。

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