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Method and structure for testing embedded cores based system-on-a-chip

机译:基于片上系统的嵌入式内核测试方法和结构

摘要

A method of testing embedded cores in an integrated circuit chip having a microprocessor core, a memory core and other functional cores therein. The method includes the steps of; forming a plurality of registers in the integrated circuit chip, testing the microprocessor core by executing its instructions multiple times with pseudo random data and evaluating the results by comparing simulation results, applying a test program to the microprocessor core to generate a memory test pattern by the microprocessor core, applying the memory test pattern to the memory core by the microprocessor core and evaluating the response of the memory core by the microprocessor core, and testing the other functional cores by applying a function specific test pattern thereto by the microprocessor core and evaluating the resultant output signals of the functional cores.
机译:一种测试集成电路芯片中嵌入式内核的方法,该集成电路芯片中具有微处理器内核,存储器内核和其他功能内核。该方法包括以下步骤:在集成电路芯片中形成多个寄存器,通过使用伪随机数据多次执行其指令来测试微处理器内核,并通过比较仿真结果评估结果,将测试程序应用于微处理器内核以通过微处理器产生存储器测试模式。微处理器核心,通过微处理器核心将存储器测试模式应用于存储器核心,并通过微处理器核心评估存储器核心的响应,并通过微处理器核心对其应用功能特定的测试模式并评估处理器的功能来测试其他功能核心。功能核心的最终输出信号。

著录项

  • 公开/公告号US6249893B1

    专利类型

  • 公开/公告日2001-06-19

    原文格式PDF

  • 申请/专利权人 ADVANTEST CORP.;

    申请/专利号US19980183033

  • 发明设计人 HIROAKI YAMOTO;ROCHIT RAJSUMAN;

    申请日1998-10-30

  • 分类号G06F110/00;

  • 国家 US

  • 入库时间 2022-08-22 01:04:01

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