Generalized theory of logical effort for look-up table based delay models using capacitance ratio

摘要

A method for designing a sequence of logic gates in a path is described. In one embodiment, the method includes modeling gate delay as a function of input slew and output load using a delay model and adjusting electrical efforts in each stage to reduce the gate delay along the path. In one embodiment, the electrical efforts in each stage are adjusted to minimize the delay along the path, where the delay along the path is minimized when a product of logical effort and electrical effort associated with each gate is the same.