首页> 外国专利> REDUNDANT LOGIC CIRCUIT HAVING DEVICE CHARGED MODEL ESD BREAKDOWN PROTECTING CIRCUIT

REDUNDANT LOGIC CIRCUIT HAVING DEVICE CHARGED MODEL ESD BREAKDOWN PROTECTING CIRCUIT

机译:冗余逻辑电路具有带电模式的ESD击穿保护电路

摘要

PROBLEM TO BE SOLVED: To provide a device charged model ESD breakdown protecting redundant logic circuit wherein a redundant logic transistor can be surely protected to electrostatic discharge of a device charged model.;SOLUTION: In the case that an electronic device which mounts the device charged model ESD breakdown protecting redundant logic circuit is subjected to electrostatic discharge of the device charged model, a diode 13 is inserted between a gate and a source of a P-type MOS transistor 11, and a diode 14 is inserted between a gate and a source of an N-type MOS transistor 12. Consequently, potentials of the gate terminals and the source terminals of the respective transistors are charged to the same potential instantaneously, and constitution for preventing electrostatic breakdown which is to be caused by the potential difference between the gate and the source is obtained.;COPYRIGHT: (C)2002,JPO
机译:解决的问题:提供一种设备充电模型ESD击穿保护冗余逻辑电路,其中可以肯定地保护冗余逻辑晶体管免受设备充电模型的静电放电的影响;解决方案:在安装了设备充电模型的电子设备中对模型ESD击穿保护冗余逻辑电路进行装置充电模型的静电放电,在P型MOS晶体管11的栅极和源极之间插入一个二极管13,在栅极和源极之间插入一个二极管14因此,各个晶体管的栅极端子和源极端子的电位瞬时被充电到相同的电位,并且用于防止由栅极之间的电位差引起的静电击穿的构造。并获得了来源。;版权:(C)2002,JPO

著录项

  • 公开/公告号JP2002246555A

    专利类型

  • 公开/公告日2002-08-30

    原文格式PDF

  • 申请/专利权人 SEIKO INSTRUMENTS INC;

    申请/专利号JP20010041568

  • 发明设计人 ISHII TOSHIKI;

    申请日2001-02-19

  • 分类号H01L27/04;H01L21/822;H01L21/8238;H01L27/092;

  • 国家 JP

  • 入库时间 2022-08-22 00:55:23

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